田　嘉，王　偉，史平彥

(空間電子信息技術(shù)研究院，陜西　西安　710100)

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室內(nèi)低信噪比BDS B1I信號(hào)高靈敏度捕獲方法

田嘉，王偉，史平彥

(空間電子信息技術(shù)研究院，陜西西安710100)

針對(duì)在低功耗、小體積及有限FPGA(Field-Programmable Gate Array)資源的平臺(tái)下，當(dāng)前BDS B1I信號(hào)捕獲靈敏度較低的問(wèn)題，基于實(shí)際信號(hào)的具體實(shí)現(xiàn)，提出室內(nèi)低信噪比BDS B1I高靈敏度捕獲方法。實(shí)驗(yàn)結(jié)果證明，應(yīng)用該方法可以在有限的資源下完成低至15 dB·Hz BDS B1I信號(hào)的成功捕獲。該成果可為在有限FPGA資源下捕獲室內(nèi)低信噪比BDS B1I信號(hào)提供參考。

BDS B1I；高靈敏度捕獲；FPGA實(shí)現(xiàn)

0　Introduction

As a new global navigation satellite system(GNSS)，BeiDou navigation satellite system(BDS)arouses more and more attention all over the world because of its continuous pace to a full constellation.Just like other GNSS receiver，BDS receiver also needs to acquire and track the pseudo-random number (PRN) code and carrier signal from BDS satellites.The function of acquisition is to estimate the PRN code，code phase and Doppler shift via a 3D search，from which these values are then sent to initiate tracking part，which continuously updates them[1].

It is difficult to acquire and track when the signal is very low.However in critical cases，like indoor，canyon and forest，the received GNSS signals are very weak.Therefore，in order to broaden the application range of BDS receiver，high sensitivity acquisition and tracking methods needs to be developed，especially when the platform is restricted to limited FPGA resource and power.

This paper aims to develop an acquisition method that can achieve a good balance between sensitivity performance and FPGA resource. Section 1 presents the real case analysis，while section 2 shows the acquisition structure which can be used to deal with the data bit and Newman Hoffman (NH) code.Then the theoretical analysis based on this structure for the determination of optimal coherent and non-coherent integration times is discussed in section 3 and proved by MATLAB simulation.Finally，based on real FPGA resource estimation，the balanced structure is presented in Section 4.

1　Real case analysis

According to [2]，when the satellite’s vertical angle is greater than 5 degree and RHCP receiving antenna gain is 0 dBi，the minimum user-received signal power is specified to be -163 dB·W (-133 dB·m).

For most GNSS commercial receivers，a perfect 3 dBi receiver antenna gain is common[3]，so it’s reasonable to assume the antenna gain of BDS receiver is 3 dBi.

Compared with forest and canyon，indoor situation is more common.Therefore，the indoor case is focused in this paper.

Tab.1 contains a 1997 study of the national institute of standards technology (NIST) about the attenuation of typical construction materials[4].The min，median and max value are shown in Table 1，since there were many varieties of most materials in the study[3]，and the median value is more meaningful than the others.In this paper，two cases are considered，one is office (dual-layer metal tinted glass)，and the other is home(concrete).Therefore，the attenuations chosen here are 20 dB and 29 dB.

Tab.1Signal Attenuation through Different Materials

Because of the existing of low noise amplifier (LNA)，the noise figure of total front-end including cable and LNA is limited，which is considered 2 dB here[5].Using Friis’s formula，the effective temperature of the entire front-end can be calculated by Eq.(1).

Teff=TA+(F-1)T0

(1)

Where TAis the effective temperature of antenna，which is 130 K[6]，F(xiàn) is the noise figure of total front-end (dB) and T0is the ambient front-end temperature (290 K).

Therefore，the noise power density can be got by Eq.(2).

N0=10×log10(k×Teff)(dB·W·Hz-1)

(2)

Where k is Boltzmann constant.So the summery of the real case analysis can be seen in Tab.2.

2　Acquisition structure

The selected acquisition method of B1I signal is the double block zero padding (DBZP) proposed in [7]to handle the bit transition due to the data and NH code，which is much suitable for the acquisition of the BDS B1I signal.

However，in very high sensitivity situation，long coherent integration time need decreasing the squaring loss[8].So in order to achieve the maximum coherent integration time of B1I (20 ms)，F(xiàn)igure 1 displays its acquisition structure.

The function of control module is keeping each start of coherent integration of the 20 branches delayed by 1 ms.Therefore，in one branch，the NH code can be completely removed and 20 ms coherent integration time can be achieved.

The peak extraction module calculates the peak value，peak index，mean value and standard deviation value.The determination module calculates the SNR of each branch and selects the biggest one，which means the NH code is synchronized with the input data.

Fig.1　Acquisition Structure of BDS B1I

3　Theoretical analysis and MATLAB simulation

According to the analysis in section 2，we know that the coherent integration time is 20 ms，and the corresponding frequency search step between two Doppler bins is 25 Hz.The evaluation of the total integration time is based on [3]and [9]，to make the acquisition successfully，the SNR after the correlation should be higher than 14 dB.

Normally，the sampling rate of analog-to-digital converter (ADC) is relatively high，so in order to decrease the calculation burden，a downsampling (down convert，low-pass filter and decimation) is performed before the acquisition process.After the downsampling，the sampling frequency is 8.192 MHz for the B1I signal.

For commercial GNSS receiver，the quantization length of ADC is always 2 bits or 4 bits.Considering high sensitivity application，4 bits quantization length is chosen here.

The results of the theoretical analysis are summarized in Tab.3.

It can be seen that the non-coherent integration times are 6 for 24 dB·Hz and 200 for 15 dB·Hz to ensure a successful acquisition.

For the purpose of proving the method presented in Fig.1，the original data is generated and added with noise by MATLAB，which is then sent to the acquisition module to check whether the correct acquisition can be achieved.The acquisition results of 24 dB·Hz are shown in Fig.2 and Fig.3，F(xiàn)ig.2 indicates the code phase and Doppler frequency are acquired correctly and Fig.3 explains the NH code of 19thbranch is synchronized with the input NH code.

Tab.3　Theoretical Analysis of BDS B1I Signal

Fig.2 Acquisition Result of CAF (24 dB·Hz)

Fig.3 Final SNR of Each Branch (24 dB·Hz)

Similarly，the acquisition results of 15 dB·Hz are shown in Fig.4 and Fig.5，F(xiàn)ig.4 indicates the correct acquisition of code phase and Doppler frequency and Fig.5 explains the NH code of 14thbranch is synchronized with the input NH code.

Fig.4　Acquisition Result of CAF (15 dB·Hz)

Fig.5　Final SNR of Each Branch (15 dB·Hz)

4　FPGA resource optimization method

Based on the commercial platform，the sensitivity performance of the current BDS receiver product is not very good which cannot satisfy the indoor application[10].The purpose of this chapter is to find a reasonable way to implement the presented acquisition algorithm in the commercial platform.The chosen FPGA board is the Terasic DE3 platform[11]，which embeds an Altera Stratix III FPGA (EP3SE260F1152).The resources available in this FPGA are：135 200 adaptive logic modules (ALMs)，equivalent to 254 400 logic elements (LEs)；864 blocks of 9 216 bits (M9K)；48 blocks of 147 456 bits (M144 K = 16 M 9K)；768 18-bit multipliers (digital signal processing，DSP).

Normally，for a project design，85% of the FPGA resource can be used，and considering the other functions in FPGA such as tracking part，management part and processor，etc.it is reasonable to assume 50% of total applicable resource can be used in acquisition，because acquisition consumes most resources compared with other modules.Therefore，the resource threshold for acquisition is 42.5% of the ALMs，random-access memory (RAM) and DSP.

The required FPGA resources of each module in Fig.1 are given in Tab.4，according to the models described in [12].

Tab.4　Resources Required for BDSB1I Acquisition (Fig.1)

The details of fast Fourier transformation (FFT) and inverse fast Fourier transformation (IFFT) implemented in FPGA are presented in Tab.5.The reason that transform length is 16 384 is because DBZP method is used here.

Tab.5　Implementation Details of FFT and IFFT

The information about the implementation of other modules is shown as：

1) The carrier and code generator are based on a numerically controlled oscillator (NCO).

2) The magnitude is computed using the Robertson approximation.

3)The coherent and non-coherent accumulator are memory-based.

Therefore，with different branches，the resources needed for the acquisition structure in Fig.1 are different，which are shown in Tab.6.It can be seen that RAM is the biggest constrain for the whole acquisition structure design.

Tab.6　Acquisition Resources Needed with Different Branches　(%)

According to the resource threshold mentioned above，five branches structure is chosen as the balanced FPGA implementation structure，which is shown in Fig.6.Though best compromise with FPGA，the drawback of this balanced structure is the longer acquisition time.But fortunately，with the assistance of internet and cell phone network，the frequency search space can be decreased to at least ±630 Hz[3]，so the acquisition time can be calculated by Eq.(3).

TA=TI+4NFBTFBNDBZP

(3)

Fig.6 Balanced acquisition structure where TIis the time required for saving the data，NFBis the number of frequency bins to be searched which is 51 here，TFBis the time needed to search one frequency bin and NDBZPis the factor caused by DBZP which is 2 here.

TFBis defined as

(4)

where fs,B1Iis the sapling rate of BDS B1I after downsampling and fFPGAis the processing frequency of the FPGA which is 204.8 MHz in our implementation.

Therefore，the acquisition time of each PRN is 2.07 s for 24 dB·Hz and 69.2 s for 15 dB·Hz.

5　Conclusion

In this paper，the high sensitivity acquisition method of BDS B1I signal based on real case analysis is presented，which can acquire the signal down to 15 dB·Hz.To validate this method，theoretical analysis and MATLAB simulation are performed.Finally，the FPGA resource optimization structure is presented.

It shows that the new proposed structure has a good compromise between sensitivity performance，F(xiàn)PGA resource and acquisition time，which is important for a mass-market BDS receiver.In order to further increase sensitivity performance and decrease acquisition time，the coupling system will be studied (i.e.BDS+INS).

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BDS B1I high sensitivity acquisition method based on indoor low signal-to-noise ratio condition

TIAN Jia，WANG Wei，SHI Pingyan

(CAST-Xi’an Institute of Space Radio Technology， Xi’an， Shanxi 710100，China)

Aiming at the problem that the acquisition sensitivity performance of current BDS B1I signal is not very well with the platform of low power，small volume and restricted FPGA resource，the paper proposed the BDS B1I high sensitivity acquisition method in the indoor low signal-to-noise ratio (SNR) condition based on the implementations of real signals.Experimental result showed that the method could help achieve the successful acquisition of BDS B1I signal at very low SNR (15 dB·Hz)，which would provide a reference for the indoor low SNR acquisition with limited FPGA resource.

BDS B1I；high sensitivity acquisition；FPGA implementation

2016-01-14

田嘉(1987—)，男，陜西西安人，碩士，工程師，研究方向?yàn)榭臻g通信與導(dǎo)航技術(shù)。

10.16547/j.cnki.10-1096.20160310.

P228

A

2095-4999(2016)03-0045-06

引文格式：田嘉，王偉，史平彥.室內(nèi)低信噪比BDS B1I信號(hào)高靈敏度捕獲方法[J].導(dǎo)航定位學(xué)報(bào)，2016，4(3)：45-50.(TIAN Jia，WANG Wei，SHI Pingyan.BDS B1I high sensitivity acquisition method based on indoor low signal-to-noise ratio condition[J].Journal of Navigation and Positioning，2016，4(3)：45-50.)