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Microwave Power Devices Department，Nanjing Electronic Devices Institute，Nanjing 210016，P.R.China

Abstract: For high-voltage and high-power Gallium Nitride（GaN）power amplifiers，a drain modulation circuit with rapid rise and fall time is proposed in this paper.To decrease the rise and fall time，the high-side bootstrap drive circuit with an auxiliary discharge switch is proposed.The effect of the parasitics is analyzed based on calculation and the parallel bonding is proposed.The storage capacitance of power supply is calculated quantitatively to provide large pulse current.To ensure safe operation of the power amplifier，the circuit topology with the dead-time control and sequential control is proposed.Finally，a prototype is built to verify the drain modulation circuit design.The experiments prove that the rise time and fall time of the output pulse signal are both less than 100 ns.

Key words：drain modulation；GaN；high voltage；power amplifier；parasitic inductance；N-MOS driver

0 Introduction

Pulsed solid-state amplifiers is replacing tubes in the fields of radar and wireless communications in recent years［1-2］.To further meet the growing de?mand for high power，high efficiency and wide band?width，Gallium Nitride high-electron mobility tran?sistors（GaN HEMTs）as a typical example of the third-generation semiconductor devices has been ap?plied［3-4］.Compared with the gate modulation，the drain modulation improves the heat dissipation of the power amplifier and is immune to slight fluctua?tions，which is widely applied［5-6］.

However，the conventional drain modulation is 28 V and less than 30 A，whose rise/fall time is more than 200 ns［7］.For 80 V kW-level GaN pulsed power amplifier，the volume of the conventional P?type metal oxide semiconductor field effect tran?sistor（P-MOS）drain modulation scheme is too large［8-9］.Besides，due to the narrow pulse width，the rise and fall time of less than 100 ns is essential，which can hardly satisfied with the traditional topolo?gy.Therefore，it is necessary to develop a reliable modulation circuit for high-voltage and large-current GaN power amplifiers.

1 Proposed Drain Modulation Cir?cuit

Table 1 shows the specifications of the de?signed modulation circuit for the GaN power amplifi?er.The operating voltage is 80 V，the peak current is up to 160 A，and the rise and fall time should be less than 100 ns.

Table 1 Specifications of drain modulation circuit

For traditional drain modulation circuit，the voltage is low and thus P-MOS is used［10-11］.Com?pared with P-MOS，the drive circuit of N?type met?al oxide semiconductor field effect transistor（NMOS）is much more difficult［12-13］.Besides，the de?manding rise/fall time and large peak current add to the difficulty of design.

As shown in Fig.1，a drain modulation circuit for high-voltage GaN power amplifiers is proposed.The circuit is composed of the power supply block，main switch block，discharge circuit block，control block and driver block.

Fig.1 The proposed drain modulation circuit

To meet the rise and fall time demand of the output voltageVDD，the proper driver chip and main switchQmainfor high voltage application are chosen based on theoretical calculation.To further decrease the fall time，an auxiliary switchQauxand auxiliary resistorRauxare added to the drain modulation circuit as the discharge circuit.The influence of the parasit?ic inductanceLleakand stabilizing capacitorCeare an?alyzed，and the parallel bonding is proposed to re?duce the parasitic influence，which can optimize the rise and fall time.Besides，to minimize the voltage overshoot caused by the parasitics，the storage ca?pacitanceCsis designed.As to the control law，the time sequential control and dead-time control are de?signed with discrete devices to ensure proper opera?tion of the power amplifier.

2 Design of Drive Circuit

The turn-on and turn-off procedure is shown in Fig.2.During the turn-on process，the gate drive currentIg_oncharges the capacitanceCgsandCgd.Dur?ing the turn-off process，the gate drive currentIg_offdischarges the capacitanceCgsandCgd.To achieve faster rising and falling edge，increasing driving cur?rent is the first priority.

Fig.2 Turn-on and turn-off procedure

The approximate switching time can be calcu?lated as

whereQgsis the gate to source charge，Qgdthe gate to drain charge，andIgthe gate drive current.

It can be seen that the switching time depends on the intrinsic characteristics of the main switch and the gate drive current.To decrease the switch?ing time，the gate charge of the chosen main switch should be small and the gate drive current should be as large as possible.

Even a large-current driver is chosen，the fall time can still be large due to the charging process ofCds.To further decrease the fall time，an auxiliary branch with a switch and resistor is proposed as the discharge circuit to provide a low-impedance dis?charge loop.Fig.3 compares the fall time between the conventional topology and the proposed topolo?gy.It can be seen that the fall time is decreased dra?matically from 62 ns to 6 ns with the proposed topol?ogy when the load is 50 Ω.

Fig.3 Comparison of fall time between different topolo?gies

In addition，a bootstrap structure is adopted for high voltage N-MOS driving circuit.When the main switch is turned off，the boot capacitor is charged to the supply voltageVccthrough the bootstrap charge loop shown in Fig.4.When the main switchQmainis turned on，the boot capacitorCbprovides the levelshifted voltage.The bootstrap diodeDbshould be fast recovery，especially when the switching fre?quency is high.

Fig.4 Boot-strap drive circuit for the main switch

To provide enough charge during the high-side drive cycle，the bootstrap capacitanceCBshould sat?isfy the following equation

whereQgis the total gate charge forQmain，tmaxthe maximum time whenQauxis off，and ΔVCBthe al?lowable ripple.

The bootstrap resistorRBis to limit inrush cur?rent at startup，and the resistance is

wheretminis the minimum time whenQauxis on.

The peak current of the diodeIpkshould be

whereVDDis the supply voltage，andVFthe diode forward voltage drop.

3 Analysis Considering Parasitics

The parasitics induced by printed circuit board（PCB）layout and bonding are unavoidable.As a re?sult，the output voltage drop and even oscillation are caused.To ensure the rise and fall time of the drain modulation circuit，the effect of the parasitics is analyzed and the parallel bonding is proposed to minimize the parasitic inductance.The storage ca?pacitance of the power supply is designed to de?crease the output voltage drop.

3.1 Parasitic inductance analysis

Typically，the radio-frequency（RF）circuit and the drain modulation circuit are bonded by the terminals，which induces the parasitics.Therefore，the rising and falling edge are affected seriously.To optimize the output characteristics of the proposed drain modulation circuit，the influence of parasitics analyzed and simulated.

The equivalent circuit of the proposed circuit is shown in Fig.5.whereCossis the parasitic capaci?tance ofQmainandRois the load.

The output voltageVDDcan be analyzed and calculated as follows.Apply Kirchhoff’s voltage law（KVL）and Kirchhoff’s current law（KCL）to the equivalent circuit

whereiL（t）is the parasitic inductance current，the voltage ofCe，andthe voltage ofCoss.

Combine above the equations and differentiate both sides of the equation

Taking the Laplace transform of Eq.（7），we have

IL（s）can be solved as

Take the inverse Laplace transform，andiL（t）is

where the expression of constantmis

So the output voltageVDD（t）is

With Eq.（12），the relationship between the output voltageVDDand the parasitic components of the drain modulation circuit can be known.The rise and fall time and the output oscillation are affected by the parasitics.

Comparing the output voltage waveforms with different parasitics by simulation，the schematic dia?gram is shown in Fig.6.The power supply voltage of the simulated circuit is 80 V，the storage capaci?tance is 200 μF and the load is 1.5 Ω.The stabilizing capacitor is equivalent toCe.SmallCemay cause os?cillation and instability of the power amplifier.The parasitic inductor is equivalent toLleak.

Fig.6 Schematic diagram of simulation

SettingCeas 100 pF，and the simulation re?sults are compared with the parasitic inductance of 0.5，2，3.5 and 5 nH.The simulated waveforms are shown in Fig.7.

Fig.7 Simulated output voltage with different Lleak

When the parasitic inductance is small，such as 0.5 nH，the output voltage is perfect and there is no oscillation.As the parasitic inductance increases，the output voltage tends to oscillate when the input signal of the drain modulation circuit is at low level.The oscillation can lead to the disruption of the pow?er amplifier output，and thus should be minimized.

So，the bonding procedure should be con?trolled to minimize the parasitic inductance，such as parallel bonding wires.The output characteristics can be studied according to Eq.（12）to determine the range of parasitics during design stage.

The value of capacitanceCefor stability should be chosen carefully as well.WhenCeis too small，the power amplifier would be unstable，as shown in Fig.8（a）.But whenCeis too large，the falling edge would be too slow and the drain modulation circuit still operates without the input signal，as shown in Fig.8（b）.

Fig.8 Simulated output voltage with different Ce (Lleak=2 nH)

3.2 Storage capacitor design

Due to the limited DC voltage source and para?sitic inductive effect，the output voltage drops when the drain current changes dramatically.To keep the output voltage，the direct current power source should be designed according to the peak current.However，the volume is seriously increased and un?necessary power loss is produced under this condi?tion.Another method is to design the storage capaci?torCsproperly to provide the instantaneous large current.

The storage capacitor is charged toVinby the DC voltage source when the power amplifier does not operate.Since the needed current during the pulse is provided by the storage capacitor，the volt?age of the power amplifierVDDis

Express the voltage drop ratioσas

Assuming that the drain current is constant dur?ing the pulse，then the designed storage capacitance can be calculated according to the following equa?tion.

whereIpis the peak current andTthe pulse width.

As to the implementation of the storage capaci?tor，the tantalum capacitors or electrolytic capaci?tors with high value are selected.However，their withstand voltage is low.To meet the requirements of 100 V high voltage，two capacitors are connected in series.Moreover，the parasitic inductance and re?sistance of these polarity capacitors（C2—C5）are usually large，which can cause the increase of rise time of the output modulation signal.To solve the problem，a ceramic capacitor with the small parasit?icsC1is connected to the polarity capacitors in paral?lel，as shown in Fig.9.

Fig.9 Implementation of storage capacitor

4 Proposed Control Circuit

Without proper control circuit，the whole sys?tem would break.Since GaN power amplifier can burn up without negative gate voltage，additional se?quential circuit is critical for operation.Besides，to prevent shoot-through of the main switch and the auxiliary switch，a dead-time control is implement?ed.The control block diagram is shown in Fig.10.

4.1 Sequential circuit design

There are strict sequence restrictions when the GaN power amplifier is powered on.When the gate voltage of the depletion GaN HEMT is zero，the drain current is very large，which can lead to the fail?ure of GaN device.So，the drain voltage should be applied only when the gate voltage of the GaN HEMT is negative.And the power-off sequence is the opposite.Therefore，it is necessary to design a sequential control circuit for protection，as shown in Fig.11.With the proposed sequential control cir?cuit，there would be no drain voltage without nega?tive gate voltage of GaN.

Fig.11 Sequential control circuit

The principle of the sequential control circuit is as follows.When the gate voltage of the GaN power amplifierVEEis negative，the voltageVFis also neg?ative.When the base to emitter voltageVbeof the triode is greater than the threshold voltage，Q1is turned on.The voltageVIis

So the gate to source voltage ofQ2is negative，andQ2is turned off.Under this condition，the out?put voltage isVTTLand the proposed drain modula?tion circuit works，as shown in Fig.12（a）.Similar?ly，as shown in Fig.12（b），when the gate voltage of the GaN power amplifier is zero，Q1is off andQ2is on.Therefore，the output voltage is 0，and the modulation circuit would not work.

Fig.12 Operation modes of the proposed sequential circuit

Based on above analysis，the designed sequen?tial control circuit ensures the proper sequence of the GaN power amplifier.

4.2 Dead?time control design

To prevent failure caused by the shootthrough，a dead-time control is applied to the main switchQmainand the discharge switchQaux.The deadtime control circuit is shown in Fig.13，which con?sists of two voltage dividers，two RC delay circuits，a non-inverting hysteresis comparator and an invert?ing hysteresis comparator.

Fig.13 Dead-time control circuit

Assuming that two threshold voltages of the hysteresis comparators areVLandVH.When the output voltage of the hysteresis comparator jumps to high level，the input threshold voltage is

Similarly，when the output voltage jumps from high level to low level，the input threshold voltage is

For the inverting hysteresis comparator，the in?put threshold voltages can be derived in the same way.As shown in Fig.14，the dead-time control is realized by the voltage difference betweenVTH2andVTH4，andVTH1andVTH3.

Fig.14 Waveforms of the dead-time control

To adjust the dead-time，the capacitanceC6andC7is changed.And the dead time can be calcu?lated as

5 Efficiency of the Proposed Topol?ogy

5.1 Power amplifier

Power amplifiers are classified into linear pow?er amplifiers such as Class A，Class B and Class C，and nonlinear power amplifiers such as Class D，Class E and Class F［14-15］.The nonlinear power am?plifiers have significantly higher efficiency than the classical linear power amplifiers［16-17］.

An overview of the ideal performance of differ?ent types of power amplifiers is shown in Table 2，whereδis the waveform factor，ηthe efficiency andPmaxthe power output capability.Considering the overall efficiency，the nonlinear amplifier classes are preferred.

Table 2 Performance of common amplifiers[18]

5.2 Power supply

The loss of the drain modulation circuit is main?ly decided by the main switch，which includes the driving loss，the switching loss and the conduction loss［19］.The loss is calculated by the following equa?tions

wherePgis the driving loss，Vgthe driving voltage，fsthe switching frequency，Pswitchthe switching loss，Ponthe conduction loss，Rdsonthe on-resistance of the switch andIQthe switch current.

The total loss of the drain modulation circuit is

The individual loss obtained from Eqs.（21—23）is shown in Fig.15.It is noted that the maxi?mum loss is the conduction loss，and thus the in?creased voltage of 80 V can dramatically decrease the overall loss.The conduction loss of 80 V is only 14% of the conduction loss of 30 V.So，the in?creased input voltage is significant for miniaturiza?tion.

Fig.15 Calculated loss(Vin=80 V, fs=10 kHz)

6 Experimental Results

In order to verify the proposed drain modula?tion circuit，a prototype is built，as shown in Fig.16.The tantalum capacitors and the ceramic ca?pacitors are connected in parallel to serve as the stor?age capacitor.The main switch is the 100 V NMOS from Infineon.

Fig.16 Prototype of the proposed drain modulation circuit

The results of the output signal are shown in Fig.17.It can be seen that the rise time and fall time of the output pulse signal are both less than 100 ns，which satisfies the requirements.

Fig.17 Experimental waveforms

The comparison of different modulation schemes is shown in Table 3.Compared with the gate modulation，the reliability of the proposed drain modulation circuit is high，the rise and fall time are small，and the power amplifier loss in standby is small.

Table 3 Comparison of different modulation schemes

7 Conclusions

A drain modulation circuit with rapid rise and fall time for 80 V kW level GaN power amplifier is proposed.The drive circuit including a bootstrap structure is adopted for high voltage N-MOS.To further decrease falling edge，an auxiliary switch is added as the discharge circuit.The effect of the para?sitic inductance on the rise and fall time is analyzed and the parallel bonding is proposed to minimize the parasitics.The capacitors are selected according to the derived equations to decrease voltage drop and oscillation.As to the control law，a sequential con?trol circuit with discrete components is designed to ensure proper sequence of gate voltage and drain voltage for the power amplifier，and a dead-time control circuit composed of hysteresis comparator is added to prevent shoot-through.Finally，an 80 V prototype is built.The rise time is 55 ns and the fall time is 72 ns，which can satisfy the requirement of less than 100 ns.