Lan Bi, Yixu Yao, Qimeng Jiang,?, Sen Huang,?, Xinhua Wang, Hao Jin, Xinyue Dai,Zhengyuan Xu, Jie Fan, Haibo Yin, Ke Wei, and Xinyu Liu

1High-Frequency High-Voltage Device and Integrated Circuits R&D Center, Institute of Microelectronics, Chinese Academy of Sciences,Beijing 100029, China

2Institute of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China

Abstract: Parasitic capacitances associated with overhangs of the T-shape-gate enhancement-mode (E-mode) GaN-based power device, were investigated by frequency/voltage-dependent capacitance–voltage and inductive-load switching measurements. The overhang capacitances induce a pinch-off voltage distinguished from that of the E-mode channel capacitance in the gate capacitance and the gate–drain capacitance characteristic curves. Frequency- and voltage-dependent tests confirm the instability caused by the trapping of interface/bulk states in the LPCVD-SiNx passivation dielectric. Circuit-level double pulse measurement also reveals its impact on switching transition for power switching applications.

Key words: AlGaN/GaN MIS-HEMTs; enhancement-mode; T-shape gate; parasitic capacitance; trapping/de-trapping; capacitance-voltage hysteresis

1.Introduction

AlGaN/GaN high-electron mobility transistors (HEMTs) or metal–insulator–semiconductor HEMTs (MIS-HEMTs), by virtue of the superior polarization-induced high mobility 2-D electron gas (2DEG), are well-proposed for their high switching speed, low parasitic parameters and low on-resistance, and have achieved recognized success in both high frequency RF and power switching applications[1?4]. Gate- and/or sourcefield plates above thick passivation dielectrics like SiNx, are commonly implemented to alleviate the high electric field in the gate-drain region and obtain higher breakdown voltage[5–7]. They are also contributed to the suppression of surface-state-introduced current collapse[5,8]. However, the field plates structure will introduce extra parasitic capacitances, leading to higherVDS×IDSpower loss and longer switching duration. In addition, the passivation layer will also bring in the passivation dielectric/(Al)GaN interface states and even bulk states in the dielectric itself. Their trapping/de-trapping processes cause the dynamic shifts of parasitic capacitances,leading to disordered ON-OFF transition and failure of dV/dtcontrol in practical applications[9–11].

In this work, gate-related parasitic capacitances of the Tshape-gate E-mode AlGaN/GaN HEMT were investigated by high-frequencyC–Vmeasurements as well as the inductive switching measurement, whereCGDwas individually observed during the Miller plateau. The instability ofCGD,caused by the trapping/de-trapping of deep interface/bulk states in LPCVD-SiNxdielectric in the gate overhang region[12], was characterized by voltage-dependentC–Vmeasurements.

2.Device fabrication and characteristics of Emode MIS-HEMT

The E-mode MIS-HEMT was fabricated on an ultra-thin-barrier (UTB) AlGaN/GaN heterostructure grown on the Si substrate[13,14]. The UTB AlGaN consists of a 1-nm AlN interlayer,a 3-nm Al0.25Ga0.75N barrier layer and a 1.5-nm GaN cap layer.Fig. 1(a) shows the schematic structure of the E-mode MISHEMT. A 10-nm LPCVD-grown SiNxpassivation layer was able to recover the 2DEG at the UTB-AlGaN/GaN interface in the access region[15], featuring a sheet resistance of 545 ?/□. The LPCVD-SiNxin the gate region was etched by fluorine-based plasma. Then in-situ NH3/N2remote plasma pretreatment was utilized to improve the etched (Al)GaN surface[16], followed by the gate dielectric deposition. The gate dielectric stack consists of a 3-nm atomic layer deposited (ALD) SiNxlayer and a 15-nm ALD-Al2O3layer with an ozone precursor, followed by the evaporation of a Ni/Au bilayer gate metal. The fabricated E-mode MIS-HEMT features a total gate width of 1 mm, a gate length of 1μm, a source-to-gate spacing of 1.75μm, and a gate-to-drain spacing of 10μm. The T-shape gate has a 0.5μm overhang on the source side and a 0.75μm overhang on the drain side, as shown in Fig. 1(b).

Fig. 2(a) shows the transfer characteristics at drain biasVDS= 1 V andVDS= 10 V. The E-mode MIS-HEMT exhibits a threshold voltageVTHof 1.26 V defined atID= 1μA with a hysteresis of 0.3 V atVDS= 1 V, indicating a decent ALD-SiNx/Al-GaN (F-etched) interface quantity. Fig. 2(b) shows the output characteristics. A saturation current of 339 mA is obtained atVGS= 8 V. Fig. 2(c) shows the three-terminal off-state currents atVGS= 0 V. A small drain leakage lower than 10–6mA is obtained and the gate leakage is always around 10 times lower.

Fig. 1. (Color online) (a) Cross sectional schematic of the E-mode AlGaN/GaN MIS-HEMT. (b) Microscope photograph of a 1-mm device.

Fig. 2. (Color online) (a) Transfer, (b) output, and (c) three-terminal off-state leakage of the 1-mm E-mode MIS-HEMT.

Fig. 3. (Color online) (a) Schematic of the gate-related capacitances in T-shape gate E-mode AlGaN/GaN MIS-HEMT. (b) Bias set of the CG–VG measurement, and (c) the multi-frequency curves of the 1-mm MIS-HEMT.

3.Gate-related capacitances and dynamic characteristics of E-mode MIS-HEMT

Fig. 3(a) shows the schematic of the gate-related capacitances in the T-shape gate E-mode AlGaN/GaN MIS-HEMT.C2is the channel capacitance performing in the E mode andC1/C3is the gate-source/drain overlay capacitance performing in the depletion mode (D mode). Multi-frequencyC–Vmeasurements were conducted on the T-shape gate E-mode MIS-HEMT with source and drain both grounded (shown in Fig. 3(b)), and theCG–VGcurves are shown in Fig. 3(c). Two pinch-off points are observed in the wholeVGrange, corresponding to different capacitance components. The first one atVG～ –10 V is related to the overhang capacitances (i.e.,C1andC3), and the second one is related to the E-mode channel (i.e.,C2). Very small frequency dispersion is observed on both E-mode gate and D-mode gate overhang, informing a high quality ALD-SiNx/(Al)GaN and LPCVD-SiNx/(Al)GaN interface. Unlike the E-mode portion, the D-mode portion exhibits a noticeable hysteresis between up- and down-sweeping curve, probably caused by deep interface/bulk states in the LPCVD-SiNxpassivation dielectric.

Fig. 4. (Color online) (a) Bias set of the CGD measurement. (b) CGD–VDG curves with varied hold and forward stressing voltage.

Fig. 5. (Color online) (a) Schematic and photo of the inductive switching circuit. (b) Waveform of the inductive switching under 50-V VBUS and (c)the turn-on transients of the DUT.

Since the Miller capacitanceCGDplays an important role on the device switching performance, in this paper,CGDwas individually investigated byC–Vmeasurement with a shorted source/gate terminal and a sweeping drain terminal, as shown in Fig. 4(a). In this measurement, drain terminal voltage (VDG) is swept from an initial voltageVinit(holding for 30 seconds beforeC–Vsweep) to 25 V and double-mode sweep was used to estimate the instability of theCGD. It is noted that a negativeVDG, corresponding to a positive bias applied on the overhang capacitor, is able to assist the spillover of the electrons to the SiNx/(Al)GaN interface as well as the trapping of the interface or dielectric bulk states. Fig. 4(b)plots the measurement results and an obvious hysteresis(> 1.5 V) on the up- and down-sweep D-mode pinch-off voltage is obtained, which is directly dependent on the magnitude of the negative stress voltageVinit. The hysteresis increases owing to the enhanced trapping in the passivation dielectric. In the down-sweep curves under different initial stress, the D-mode pinch-off voltage merges together, indicating that an efficient electrons’ de-trapping is achieved with a 25 VVDG.

In this work, to further identify the effect of the overhang capacitance on the device switching performance, a double-pulse measurement was executed with measurement setup plotted in Fig. 5(a). A device bare die was mounted on a testing PCB by conductive silver epoxy, and its pads were bonded out by golden wires. A simple gate driver circuit is used with a separate turn-on and turn-off path. In order to enlarge the Miller plateau, a 10 k? charging resistor was used to slow down the turning-on process. The waveform of inductive switching under 50 VVBUSand the turn-on transients are shown in Figs. 5(b) and 5(c). During the turn-on period of the second pulse, the presence of the D-mode portion ofCGDreduces the slew rate of output voltage, leading to a longer Miller plateau and extra switching power loss. The turning point of two sections of dVDS/dtis around 10 V in the beginning of Miller plateau, which coincides with the pinchoff voltage ofCGD.

4.Conclusion

In this work, gate-related capacitances of the T-shapegate E-mode AlGaN/GaN HEMT have been investigated byC–Vmeasurements and the inductive switching measurement. The overhang-relatedCGDexhibits a noticeable hysteresis in double sweeps, informing its sensitivity to forward stressing voltage due to the trapping of deep interface/bulk states of LPCVD-SiNxpassivation dielectrics. During the turnon period of inductive switching measurement, two sections of dVDS/dtwith a turning point around 10 V are observed for the presence of D-mode portion inCGD, leading to a longer switching transfer and higher switching power loss.

Acknowledgements

This work was supported in part by the National Natural Science Foundation of China under Grant 61822407, Grant 61527816, Grant 11634002, Grant 61631021, Grant 62074161,Grant 62004213, and Grant U20A20208; in part by the Key Research Program of Frontier Sciences, Chinese Academy of Sciences (CAS) under Grant QYZDB-SSW-JSC012; in part by the Youth Innovation Promotion Association of CAS; in part by the University of CAS; and in part by the Opening Project of Key Laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, CAS.