Ji Lianqing Xu Zhiming Zhou Jianyi Zhai Jianfeng

(State Key Laboratory of Millimeter Waves, Southeast University, Nanjing 210096, China)

The RF power amplifier tends to be the most power-hungry block for a typical transmitter system, leading to a stringent requirement for efficiency. It is a challenge to maintain high efficiency during operation over the wide instantaneous power range for modern modulation signals such as WCDMA and LTE, while meeting their demanding linearity requirements[1-2].

Switching mode PAs, such as class-E, class-F and inverse class-F[3-5]have been demonstrated to improve the efficiency, but they have the problem of poor linearity caused by the bias at cut-off, leading to severe out-of-band interference and in-band distortion. To avoid the nonlinear distortions caused by the PAs, digital predistortion (DPD) is considered as the most cost effective method among all the linearization techniques.

In the past few years, many behavioral models have been proposed to characterize the nonlinear and memory effects of the PA[6-9]. Among these models, the Volterra series model was considered as a general way to model a nonlinear system with memory, but with a high computational complexity. The dynamic deviation reduction-based Volterra series model proposed in Refs.[10-11] and the simplified visions[12-13]that followed not only significantly reduced the complexity of the Volterra series model, but also made the model parameters extraction more flexible.

In this paper, a class-F switch mode PA along with the DPD based on the simplified second-order dynamic deviation reduction-based Volterra series model[12-13]is used to optimize the PA’s intrinsic efficiency-linearity trade-off. The experimental results show that the designed digital predistorted class-F PA obtains high drain efficiency and excellent linearity for the 4-carrier WCDMA signals at an average output power of 33.3 dBm.

1 Class-F Power Amplifier Design

Ideally, the class-F PA must have all of the odd harmonics terminated with an open circuit at the intrinsic drain of the transistor to generate the squared voltage waveform and all the even harmonics with a short circuit termination for the harmonic current. However, it is not practical in the real design. In this paper, only the second and the third harmonic load impedances are considered. The topology of the circuit is shown in Fig.1.

Fig.1 Circuit topology of the class-F PA

1.1 Circuit topology

The second and the third harmonic load impedances are implemented in the output match network. The input match network provides proper harmonic impedance at the transistor’s gate to improve efficiency. A resistor serially connected on the input end is used to improve the stability of the circuit.

1.2 Implementation and measurement results

Fig.2 shows the picture of the final designed class-F PA based on the circuit parameters in Fig.1.

Fig.2 Photograph of the designed class-F PA

With the gate voltage biased at -2.8V and the drain voltage biased at 28 V, the measured PAE, the output power and the gain with the input power of 25 dBm for the frequency swept from 2.07 to 2.17 GHz are plotted in Fig.3. The PAE is greater than 60% and the output power is greater than 38 dBm in the range of 2.07 to 2.14 GHz. Fig.4 presents the measured PAE, the output power and the gain at 2.12 GHz for the input CW signal power swept from 8 to 28 dBm. A peak PAE of 75.2% is obtained with a maximum output power of 39.4 dBm.

Fig.3 Measured PAE, gain and Pout vs. input frequency with input power of 25 dBm

Fig.4 Measured PAE, gain and Pout vs. input power at 2.12 GHz

2 Digital Predistortion Experimental Results

The experimental platform set up similar to that in Refs.[5,14] is used to validate the linearity improvement of the designed class-F PA(see Fig.5). A vector signal generator (Rohde & Schwarz SMBV100A), a vector signal analyzer (Agilent N9030A), a PC with Matlab and Agilent’s 89600 vector signal analyzer (VSA) software, and the class-F PA under test constitute the open-loop DPD validation system. All the instruments and the PC are connected in a local area network (LAN), where the data can be downloaded from the Matlab to the vector signal generator and the collected data in the vector signal analyzer can be transferred to the PC by the LAN cable.

Fig.5 Experimental validation platform

The class-F PA is operated at 2.12 GHz and excited by a 4-carrier WCDMA signal with 7.1 dB PAPR. A total of 3556 I/Q samples with an oversample factor of 4 are generated in the Matlab and downloaded to the vector signal generator with a sample rate of 80×106sample/s, yielding the 20 MHz signal. The baseband I/Q signals are modulated and up-converted to 2.12 GHz in SMBV100A, and then amplified by the class-F PA. After appropriate attenuation, the output distorted signal of the PA is down-converted and demodulated by N9030A. A total of 7112 I/Q samples are captured at the output of the PA with an I/Q sample rate of 80×106sample/s. After time alignment and normalization, 3556 samples are used for model parameter extraction.

In order to accurately model the nonlinearity and memory effects, the nonlinearity order in the Volterra model is set to be 9, while the memory depth is set to be 7. Comparisons of the experimental results at different average output powers are shown in Fig.6. After DPD, the linearization results in terms with ACPR below -50 dBc are obtained at an average output power of no greater than 33.3 dBm.

Fig.6 Measured DE and ACPR with/without DPD vs. average output power level

Fig.7 presents the measured power spectral density (PSD) of the PA with and without DPD at an average output power of 33.3 dBm. The measured ACPR are decreased to -51.9 dBc (lower) and -54.0 dBc (upper) from -28.3 dBc (lower) and -27.5 dBc (upper), respectively, with a drain efficiency of 37.8%.

Fig.7 Measured PSD of the PA output with/without DPD at average output power of 33.3 dBm with drain efficiency of 37.8%

The linearized class-F PA reported in this paper with 20 MHz 4-carrier WCDMA signals is compared with a selection of comparable state-of-the-art linearized switching mode PAs as shown in Tab.1.

Tab．1 Linearized switching mode PA comparison

3 Conclusion

In this paper, a class-F power amplifier using Cree GaN HEMT CGH40010 operating at 2.12 GHz is implemented for WCDMA applications. The designed class-F PA achieves a PAE of 75.2% with an output power of 39.4 dBm. For the 20 MHz 4-carrier WCDMA signals, the ACPR is decreased to be -51.9 and -54.0 dBc by using the DPD technique with a drain efficiency of 37.8% at an average output power of 33.3 dBm.

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