Shruti Kalraand Ruby Beniwal

(Department of Electronics and Communication, Jaypee Institute of Information Technology, Noida 201307, India)

Abstract: This paper presents a physics-based compact gate delay model that includes all short-channel phenomena prevalent at the ultra-deep submicron technology node of 32 nm. To simplify calculations, the proposed model is connected to a compact α-power law-based (Sakurai-Newton) model. The model has been tested on a wide range of supply voltages. The model accurately predicts nominal delays and the delays under process variations. It has been shown that at lower technology nodes, the delay is more sensitive to threshold voltage variations, specifically at the sub-threshold operating region as compared with effective channel length variations above the threshold region.

Keywords: statistical variation; analytical model; process variability; nanoscale CMOS; propagation delay

0 Introduction

Digital circuits’ exponential scaling has led to a wide range of variation in process and design factors, causing performance uncertainty at the nanoscale technology node. Since the perfect control of photolithography and dopant quantity is difficult, process variations occur due to changes in threshold voltages and effective channel length. When both inter- and intra- die components are taken into account, effective channel length and threshold voltage can vary by up to 30% and 10%, respectively[1-2]. Process parameters, including isolation oxide strain, transistor orientation, and etch loading impact, further alter their nominal values. These parameters have been expressed statistically using appropriate distribution functions due to the stochastic character of the process changes and modelling challenges[2-4]. For example, the Gaussian distribution function is commonly employed. But because supply voltages and temperatures are unknown, they are generally regarded as corner parameters rather than random parameters. As the supply voltage is reduced to save energy, the sensitivity of delay parameters increases, and the supply voltage must be accurately evaluated in systems that handle parameter fluctuation[5-6]. In order to accommodate process variances in submicron circuit design, a delayed timing corner has been historically used to ensure all dies running at their maximum working frequency. Due to the increased variability in circuit delay at the ultra-deep submicron technology node, the minimum and maximum limitations for delay routes must be increased (i.e., the time calculated between the target obtained and the performance of the after-fabrication system). This technique may waste design resources as the number of process variables increases. To address this constraint, current research focuses on conveying the variance in gate delay across channels and identifying the probable solution of timing margins acquired[5-7]. Although the aforementioned strategies attempt to forecast minimal and maximum limits in the presence of statistical noise, their performance is dependent on the modelled fundamental gate delay variability and connection latency. MOSFET models, which serve as the basic correspondence vehicle between circuit designers and silicon foundries, play a critical part in chip outline efficiency. Although BSIM4[8]models for SPICE are well known to precisely model MOSFET, these are too complex to be used for analytical circuit design methodologies. Thus, precise physics-based efficient models that transform process parameter variation into delay variability at the circuit level are necessary for first-hand performance estimation. An analytical model capable of developing a methodology for optimum design needs to have the following features:

1) It should be small and capable of delivering analytic solutions to circuit equations for the fundamental digital building elements that make up the system’s architecture.

2) A first order short channel effect should be included in the model equation to estimate the ON drain saturation current that defines the conducting state of the MOSFET switch[9-10].

3) In scaled MOSFETs of nanometer dimension, dimensional and process variability become an integral part of design consideration. In other words, the capability to handle variability for a statistical design is an added requirement of the analytical model[11-12].

4) The model must be able to handle designs that fall into both the high performance and low power categories. To meet the current standards for digital design, it is necessary that the model be relevant for both strong and moderate inversion zones.

5) The model should not only be scalable but also predictive, allowing for early design performance evaluation at new technology nodes around channel length limitations of 10 -20 nm[13-16].

6) The parameters of the analytical model should ideally match the parameters of the compact model used for circuit simulation. This allows the hand calculation or optimized paper design generated prior to SPICE to be effortlessly transferred to industry standard circuit simulators for silicon design prototype. Additionally, such a connection aids in the understanding of simulation data. Taking the above points into consideration, the following methodology has been adopted to derive the statical model:

a) The first step in the derivation is to update the first order velocity-field relationship with the three fitting parametersa,b, andcin order to translate the accuracy of the second order hyperbolic function to the first order velocity-field relationship. The amount of time spent on analytical computations is significantly decreased as a result of this.

b) The drain current expression now includes the impacts of secondary short channel effects such as parasitic resistance and DIBL.

c) For the purpose of enabling predictions of circuit performance for future technology generations, the proposed model is linked with the simple mathematical expressions of the Sakurai-Newtonα-power law model[17]and the Predictive Technology Model (PTM)[18].

d) The physical value ofαis found by equating the saturation drain current equation obtained from the proposed model with the saturation drain current equation acquired from the SN model. In order to scale down the physical value ofαto a technology node as small as 32 nm, the PTM parameters are used.

e) In order to determine delay and its variability with changes in channel length and threshold voltage, the estimated drain current was used in conjunction with the channel length and threshold voltage estimates. The variations in channel length and threshold voltage have a substantial influence on the unpredictability of circuit delay.

f) The variability analysis was performed on the benchmark circuits ISCAS85[19]and Microelectronics Center of North Carolina (MCNC)[20]. Comparison of the mean and standard deviation obtained from the analytical findings with those obtained from Monte Carlo simulations revealed that the analytical results obtained are in close proximity with that of MC simulations.

1 Process Variation

Intrinsic and extrinsic factors contribute to process variation. Intrinsic differences are often caused by device physics limits, while extrinsic variations are produced by manufacturing faults that vary by foundry. While extrinsic differences may be minimized via improved process control, intrinsic variations are uncontrollable and serve as a significant barrier to device scalability. Significant causes of intrinsic variation include the following:

1) Random dopant fluctuation: It has been shown in the literature that the quantity and location of dopant atoms implanted are random in nature at a scaled technology node. Due to the extremely small number of dopant atoms in scaled devices, there is a significant fluctuation in the threshold voltage (which is a function of dopant concentration). When the dopant atoms are large, the Poisson distribution may be used to estimate the dopant fluctuations, as opposed to the Gaussian distribution[21-22].

2) Roughness of the line edge: This refers to the variance in the form of the gate along the channel width direction. It happens more often near the mask borders, where bigger material grains dissolve more readily than smaller material grains. The roughness of the line edge does not scale with technology and cannot be decreased via lithographic process control. However, this has an effect on the threshold voltage and leakage current of the device[23-24].

3) Oxide thickness fluctuations: When the oxide layer thickness is a few Si atom layers, the atomic scale roughness at the interface of Si-SiO2and gate SiO2produces oxide thickness variations in scaled devices. This has an effect on the carrier mobility, and therefore on the device’s threshold voltage[25-26].

All of the above-mentioned fluctuations become more significant as the technology node reduces, but random dopant fluctuations (which result in threshold variation) become increasingly crucial as the supply voltage drops. Because the variation in drain current is asymmetric at the ultra-deep submicron channel length and at lower supply voltage, statistical metrics like mean and standard deviation cannot be used to identify the shape of the distribution[27-28]. Thus, the probability distribution of drain current was studied using Skewness, a measure of asymmetry. Fig. 1 illustrates the skewness of MOSFET’s current distribution with regard to supply voltage. The findings were acquired using a Monte Carlo simulation with 20000 HSPICE nodes at the 32 nm technology node. As the supply voltage drops, the drain current varies asymmetrically owing to the change in threshold voltage, which is considerably greater than that at higher supply voltage.

Fig.1 Drain current skewness at various supply voltages for 32 nm technology node

In general, the variability of any random variable may be expressed as its standard deviation normalized by its mean (σ/μ) value, which indicates its global deviation.

2 Analysis of Circuit Performance Variability

In the past, Monte Carlo simulation of circuits has been used to study gate delay variability. Although the results are relevant, implementing them is time-consuming in practice. An alternative strategy is to implement the circuit using Response Surface Model (RSM), which raises the performance of the circuit linearly at nominal process values. Analysis of principal component technique is often used in addition to this technique to explore the various sources of statistical variation. Though this technique is only applicable to small channel transistors, the correlation between the parameters involved is quite complicated and non-linear, specifically the threshold voltage, which depends on the length of the channel. Additionally, utilizing the above two approaches (RSM and Monte Carlo), one can get only limited physical insights for improving circuit designs that are aware of variance. This paper presents an analytical modelling approach that is generalized for digital circuits and efficiently links the process variables to performance parameters. Thus, the presented model is a desirable choice for accurately and effectively forecasting delay variations at the circuit level. In order to extend the study of scalability of variability, the present model incorporates key physical phenomena that are seen at the ultra-deep sub-micron level. At any pointxacross the length of the channel, the drain current can be expressed as[29]

Ids=I(x)=WCox(VG-nV(x))v(x)

(1)

In the above equation,Wrepresents channel width,Coxrepresents capacitance of gate oxide computed per unit area, VG =Vgs-Vth, VG represents gate overdrive voltage,Vgsrepresents gate to source voltage,Vthrepresents threshold voltage,nrepresents bulk charge variation across the effective channel length,V(x) is potential in between minority charge quasi fermi potential as well as the bulk equilibrium fermi potential at pointx, andv(x) represents carrier velocity computed at pointx.The relationship between carrier velocity and the channel electric field in the inversion layer is described as

(2a)

(2b)

whereErepresents lateral electric field,μeffrepresents effective mobility,Ecis critical field measured when the carriers become velocity saturated,Mis an empirical constant,M= 2 for negative charge carriers andM=1 for positive charge carriers,υsatrepresents saturation velocity measured in m/s. SinceM=2 requires complex calculations[30], the following equation presents the modified first orderυ-Emodel. Here,M=1 anda,b,care the fitting constants described as

(3a)

(3b)

The three fitting parametersa,b,care utilized to map first order hyperbolic function to second order. By doing so, the analytical calculations involved are reduced to a large extent.μeffis a function of the gate voltage and is expressed by[31-32]

(4)

whereμ0represents low field mobility, andθis mobility degradation coefficient.

θmis the mobility degradation in the presence of parasitic resistanceRs, which can be expressed as[33]

θm=θ+β0Rs

(5)

whereβ0represents maximum device transconductance.E(x) can be written by substituting Eq. (3) in Eq. (1):

(6)

For obtaining the drain current of linear region, Eq. (6) is integrated fromx=0 tox=LandV(x)=0 toV(x)=Vds.Here,Ldenotes effective channel length. Thus, The drain current of linear region can be expressed as

(7)

It is well known that when the lateral electric field across the channelE(x) becomes equal to the value of critical electric fieldEc, the carrier velocity saturates. Thus, puttingE(x) =Ecin Eq. (6):

(8)

whereVdsatrepresents drain saturation parameter.

Equating Eq. (7) and Eq. (8) that represent drain current in linear and saturation regions respectively, there is

(9)

Roots of Eq. (9) are

(10)

where the factorζhas been introduced to avoid any instability in the mathematical computation. The value ofζis finitely very small. The above equation describesVdsateffectively and has been utilized to solve short channel drain current expressions.

In the presence of parasitic source/drain resistanceRs,Idsatis expressed as

(11)

whereIdsat0=IdsatforRs= 0.

The parasitic resistance is an important factor at ultra-deep submicron technology node. Thus, it has been included in all the calculations done further utilizingα-power calculations to obtain appropriate accuracy and prediction[29].

Another short channel effect reliant in deep submicron technology node is drain induced barrier lowering (DIBL). The effect of change in threshold voltage in the presence of DIBL can be modeled as[29]

(12)

whereVthrepresents threshold voltage at lowVds(0.1V) or nominal value ofVdsin Eq. (12),δVthrepresents difference in the threshold voltage measured at higherVds,δVth=Vth-Vth(Vds),σDIBLis DIBL parameter.

(13)

(14)

(15)

Vdsat1=Vdsat∣Vgs=Vdd

(16)

whereαrepresents velocity saturation index,Brepresents transconductance parameter,λrepresents channel length modulation parameter,Vddrepresents the supply voltage.

The logarithm graphs’ outstanding linearity demonstrates the correctness of

Idsat=B(Vgs-Vth)α

(17)

Ref. [34] incorporates the width effect and suggests the following changes in the established SN-model for the current equations in the linear and saturation region:

Idsat=K1(Vgs-Vth)α(1+λVds)

(18)

(19)

ParameterBin the SN mode was updated to factorK1and accounts for width effect.

K1=β1+β2W+β3W2

(20)

whereβ1,β2andβ3are fitting coefficients.

Thus, neglectingλin Eq. (18), the saturation drain current can be written as

Idsat=K1(Vgs-Vth)α

(21)

The value ofK1can be calculated by substituting log(Vgs-Vth) = 0.Thus, putting VG=1 in Eq. (8),

I see that this will not do, said the man; you had better spin,25 perhaps you can do that better. She sat down and tried to spin, but the hard thread soon cut her soft fingers so that the blood ran down. See, said the man, you are fit for no sort of work; I have made a bad bargain with you. Now I will try to make a business with pots and earthenware19; you must sit in the market-place26 and sell the ware20. Alas21, thought she, if any of the people from my father s kingdom come to the market and see me sitting there, selling, how they will mock me? But it was of no use, she had to yield unless she chose to die of hunger.

(22)

The physical value ofαmay be determined by puttingIdsat(Eq. (22)) = (Eq. (8)):

(23)

whereVdsatis given by Eq. (10). Thus,

(24)

The physical values ofαobtained for different technology nodes are summarized in the Table 1. It is worth noting that the value of threshold voltage obtained fromα-power model and the analytical model is not the same. Thus, the threshold voltage is repeatedly iterated with the starting value as given in PTM model[18]till the error obtained reaches less than 2% for the entire voltage range.

Table 1 Model parameters utilized for calculations

The model equations presented above are applicable in strong inversion region. But for low power circuit applications, where the circuit is operating in either weak or moderate inversion region, modification to the industry standard EKV equation[35]is proposed. The EKV model describes the drain current applicable in all regions of operations for long channel devices as

(25)

where

ids=Ids/Ispec

vgs=Vgs/UT

vth=Vth/UT

UT=KT/q

whereIds,Ispec,UT,T,qrepresent unnormalized drain current, specific current, thermal voltage, temperature and unit charge respectively.

For transistor working in moderate or weak operating regions, the following is the proposed modification model:

(26)

The value ofαcan be found through mathematical interpolation with the same procedure as described by Ref. [35].

3 Gate Delay Variability

The time delay of the CMOS inverter is calculated based on the length of time it takes to charge or discharge the load capacitance during operation. The delay of propagation (tp) of a gate can be represented as[36-40]

(27)

whereCLis the output load capacitance,IONis the ON current of MOSFET or drain whenVgs=Vds=Vdd.

ION=K1(Vdd-Vth)α

(28)

Output load capacitance is defined as the amount of intrinsic capacitance of the fan-out gates from the driving phase and is denoted byCL. As a result,CLis proportional to

CL∝CoxL(ξiWi+Wi+1)

(29)

ξirefers to the relationship between parasitic capacitance in the driver stage and input gate capacitance in the fanout stage.i-th and (i+1)-th are the driver and load stage annotations, respectively.WbecomesWiin Eq. (27) (transconductance factorK1is also width dependent as expressed in Eq. (20)). PuttingCLvalue from Eq. (29) into the given Eq. (27), there is

(30)

ForNnumbers of stages across the pathway, the path delay (PD) can be estimated as the total of gate delays. Thus,

(31)

PD=kpdVddPD(W)

(32)

wherekpdis the technology-dependent factor, and PD(W) depends on the size of the transistor that makes gate sizing along the path. Historically, delay forNstages has been expressed in terms of the average single-stage propagation delaytpand the logic depthLd.Logic depth is defined as the greatest number of fundamental logic gates that a signal may travel from source to destination in any digital circuit, PD =tpLd, but this formulation does not allow the sizing of the gate.

The gate delay given in Eq. (27) is used to investigate variability by accounting for variations in threshold voltage caused by DIBL and in specific current caused by mobility degradation. If the statistical variation in effective channel length and threshold voltage is considered to be Gaussian and there is a high correlation between transistors with small range of gate size, the variability in gate delay (σ/μ, coefficient of variation) is stated as follows:

(33)

If the circuit is extremely big and spatial correlation dependency cannot be ignored, it can be split into smaller sub-circuits and then the variability of the partitioned sub-circuits can be computed as described below.

The process parameters are stated as a sum of correlated and random components, and the total of the variances of these two components yields the process parameter’s overall variation.

Correlated variations are addressed by dividing the larger circuit as a grid and representing the variation in each square of the grid with a single random variable. To simplify the problem, the set of coupled random variables was substituted with another set of mutually independent random variables with zero mean and unit variance using principal component analysis. It is to be noted that the correlation structure of process parameters is often specified by a distance-dependent function. Using such a function to create the correlation matrix may result in non-positive-definite correlation matrices. Simple approaches, such as ignoring the correlation matrix’s negative eigenvalues, may be utilized to overcome such concerns[41]. The single gate delay is presented as follows:

(34)

wherednormis the nominal value of delay expressed by Eq. (30) ,αqrepresents sensitivity of delay to process parameters under consideration and, ΔPqis the change in the process parameters from their nominal value. For each timing arc associated with the gate, the values ofdnormandαqare determined and stored in a two-dimensional database indexed by the input transition time and output load capacitance. After partitioning the big circuit with a grid, the delay of individual gates is stated as a function of the grid’s random variables. The delay in Eq. (34) is then stated as using the principal component technique described as

(35)

The delay of each gate (Da) can therefore be expressed as

(36)

The above expression is a canonical delay expression. The nominal delay (a0) is the mean delay. Since,ziare uncorrelatedN(0,1) random variable, the delay variance can be expressed as

(37)

The covariance of delay with one of the principal components can be expressed as

(38)

Due to the fact that the random components are uncorrelated and hence do not contribute to the covariance of the delay at the two nodes corresponding to the gate’s inputs (example “a” and “b”), the covariance may be calculated as

(39)

The delay of the circuit is determined in deterministic timing analysis by applying two functions on the delay of individual gates: sum and max. Similar functions are defined as follows for the delay expression given in Eq. (36):

(40)

The maximum function is not strictly Gaussian for normally distributed random variables. According to Refs. [42-43], the maximum of two Gaussian random variables may be approximated highly accurately by another Gaussian. If

c=max(a,b)

(41)

whereaandbare Gaussian random variables, the parameterc, which is assumed to be Gaussian, may be calculated using the formulas presented in Ref. [44]. This method calculates the mean and variance ofcin terms of the means and variances ofaandb, as well as their correlation coefficients. Additionally, Ref. [44] creates equations for evaluating the correlation betweencand any other random variable in terms of the random variable’s connection withaandb.It is supposed that, in accordance with Refs. [42] and [45],cmay be stated in the same canonical form asaandb.To get the coefficients for the canonical form expression forc, the mean, variance, and correlation ofcwith the main components are matched, resulting in the following expression:

(42)

It is possible to preserve the mean and variance of the random component while avoiding scaling the correlation coefficients of the primary components to match the variance, which would result in a loss of their correlation in the space between them[42]. Additionally, Ref. [45] employs this method to account for random changes in timing analyses. The aforementioned approach is employed iteratively to find the maximum of more than two variables.

4 Model Validation

1)The suggested model represented in Eq. (30) has been validated for a variety of supply voltages as well as various threshold voltages as shown in Fig. 2 to ensure that it is accurate, whereVth0represents zero bias threshold voltage. From the image, it can be observed that the suggested model accurately predicts delays for voltages above and below the threshold voltages used in the experiment. It was necessary to verify the acquired findings using the industry standard HSPICE while taking the PTM[18]model into consideration. For the validation of this model, an error in the range of 1%-10% is considered acceptable for inaccuracy.

2)Using the suggested model expressed in Eq. (30), the delay of the CMOS inverter is further tested throughout a wide range ofLand supply voltageVdd. The result of this verification is illustrated in Fig. 3 for the 32 nm technology node. As can be seen in the image, the suggested model is verified over a broad range of channel length variations (up to 40% of the total channel length). Using the industry standard HSPICE and PTM model[18], it was required to confirm the data that had been obtained. For the purposes of validating this model, an obtained error in the range of 1%-10% is deemed acceptable in terms of inaccuracy.

Fig. 2 Relationship between the CMOS inverter gate delay with FO4 load with Vdd and L and Vth (32 nm)

Fig. 3 Relationship between nominal delay and L (32 nm)

3)The variability of the CMOS inverter is displayed in Fig. 4 by adjusting the threshold voltageLandVthsolely, the channel length only, and varying both at various supply voltages, with Monte Carlo circuit simulations, assumingLandVthfluctuations are normally distributed and the variability expression from Eq. (33). On the basis of the figure, it can be concluded that channel length differences account for around 60% of delay variations. Therefore, this proposed analytical method may be utilized for first hand investigations of delay variability. Slower gate delays are more variable at lower power supplies due to nonlinear gate delay response. Eq. (1) in Ref. [46] quantifies the trend, whereas our model accurately predicts it.

4)Further deconstruction of variability into causal physical processes is warranted given the relative importance of different sources of process variation, as indicated in Fig. 5 generated from the proposed model in Eq. (30) and presented in Fig. 5. It is obvious from the figure that threshold voltage variations caused by DIBL are the primary source of the problem, particularly at lower supply voltages. However, the transconductance factor, which takes into account the impacts of both size (W/L) and loading capacitance, is the primary source of variations in areas over the threshold.Lcontributes to these variations, which are essentially independent of supply voltageVdd.

Fig. 4 The proposed model that correctly predicts delay variability (32 nm)

Fig. 5 Individual physical processes’ contribution to variable delay (32 nm)

5) In Fig. 6,σt/tprepresents the variation in delay time represented by the CMOS inverter with FO4 load (taking into account variation of bothLandVthandL), which is calculated from the variability expression provided in Eq. (33). A decrease in the variabilityσt/tpcan be detected when the value ofσis normalized by the mean values of threshold voltage and effective channel length, as illustrated in Fig. 6. AssumingVdd=0.6 V, their contributions are essentially identical betweenVthandL. When the supply voltage is reduced, it can be observed that the change in normalizedVthis large when compared with the change inL, as seen in the figure. However, since the absolute variation ofLis greater than that of the other variables,Lcontinues to be the dominant source of variability.

Fig. 6 Sensitivity of the variation in delay due to variation in normalized effective channel length L and Vth

6)Table 2 shows the findings for the ISCAS85[19]and Microelectronics Center of North Carolina (MCNC)[20]benchmark circuits, respectively. It is shown in the table how the mean and standard deviation of delay are acquired using the suggested model and compared with those obtained using MC-based simulations. Comparison of circuits with different logic depths shows that circuits with lower logic depths exhibit more variations in delay than circuits with higher logic depths. This is due to the fact that the correlations in the random component are not taken into account, which might result in an inaccuracy in the calculated variance. It is also found that the error in delay is inversely proportional to the depth of the critical path[15]and can be expected to be small for larger circuits.

Table 2 Comparison of the proposed model with MC simulations

5 Conclusions

This paper presented an analytical model of delay variability that is physically grounded and suitable for pre-SPICE analysis. The model incorporates short channel effects of DIBL and velocity saturation and is accurate over a broad variety of supply voltageVdd, including sub-threshold. The relative significance ofVthandLvariation in terms of total digital circuit delay variability has been demonstrated and the model was used to explain the underlying physical phenomena. The obtained results lie within the acceptable range of 1%-10%.