Liang-Jian Lyu | Qing-Zhen Wang | Ze-Peng Huang | Xing Wu

Abstract—The R-2R resistor ladder is one of the best topologies for implementing compact-sized digital-to-analog converter (DAC) arrays in implantable neuro-stimulators.However,it has a limited resolution and considerable interchannel variation due to component mismatches.To avoid losing analog information,we present sub-radix-2 DAC implemented by the R-βR resistor ladder in this paper.The digital successive approximation register (DSAR)algorithm corrects the transfer function of DACs based on their actual bit weights.Furthermore,a low-cost in situ adaptive bit-weight calibration (ABC) algorithm drives the analog output error between two DACs to zero by adjusting their bit weights automatically.The simulation results show that the proposed algorithm can calibrate the non-linear transfer function of each DAC and the gain error among multiple channels in the background.

Index Terms—Digital calibration,digital-to-analog converter,gain error,in situ,mismatch,non-linearity,resistor ladder.

1.lntroduction

Current-mode neuromodulation is widely adopted in clinical and neuroscience research[1],[2].The activity of nearby neurons can be activated or suppressed by delivering current pulses to micro-electrode arrays (MEAs)placed on specific brain regions,central nerves,or peripheral nerves.Functional electrical stimulation has been successfully used in treating various types of nerve damage,including the restoration of vision[3].Fig.1shows the diagram of the artificial retina system,which receives external optical stimuli and delivers corresponding current stimulation waveforms to the optic nerves[4],[5].The artificial retina usually consists of tens to hundreds of identical pixels,and each pixel includes a photo-sensitive device,an analog front-end(AFE),a digital signal processor (DSP),and a current-mode digital-to-analog converter (DAC)[6],[7].Among them,DAC is a critical part of communications with the brain by generating programmable current pulses.Because the device is implanted on the retina,its size and power must be strictly limited.Furthermore,interchannel mismatches of the stimulators will lead to charge accumulation and permanent damage to the neural tissues.Therefore,compact-sized DACs with a high resolution are in great demand[8],[9].

The R-2R DAC uses only two resistance values ofRand 2R,and the number of the resistors is linearly proportional to the resolution of DAC,therefore it is widely adopted in designing small-area DACs[10],[11].Moreover,its simple architecture also facilizes operation under extreme conditions or implementation in non-silicon semiconductor processes[12]-[15].However,R-2R DAC has limited linearity due to the component matching,and is conventionally considered not suitable for high-resolution applications greater than 8[10].

A lot of works have been searching for calibration methods for R-2R DAC.High-resolution R-2R DAC requires high-precision tunable resistors,such as silicon-chromium thin-film resistors[16].However,such devices are not available for most processes.Reference [17] used an auxiliary R-2R ladder to compensate main DAC,the calibration accuracy is determined by the measuring instrument.Reference [18] adopted the ordered element matching (OEM) method to calibrate the gain error between different segments of DAC,but the segmentation leaded to a larger area compared with the binary-weighted resistor ladder.

In this paper,we propose an all-digital calibration method,which can dynamically correct the error between two DACs.Meanwhile,no external calibration circuits,such as the high-resolution analog-to-digital converter (ADC),are required.Therefore,the area of each DAC will be greatly reduced and making it possible for small-sized DAC arrays with a high resolution.

The rest of this paper is organized as follows.Section 2 analyzes the mismatch effects in resistor ladder DAC.Section 3 describes the proposedin situdigital background calibration algorithm.Section 4 presents behavior model simulation results to verify the effectiveness of the calibration method.Finally,Section 5 concludes this paper.

2.Mismatch Effects in R-βR DAC

Several previous works have analyzed the transfer functions of conventional R-2R DAC and its mismatch influence[19]-[21].In this paper,we extend R-2R DAC to R-βR DAC,whereβcould be any positive value.Fig.2(a) shows the schematic ofn-bit current-mode R-βR DAC.There are two types of resistors in this circuit,the “rung” resistors (i.e.,R2,k,wherek=0,1,…,n) with resistances ofR0and the “l(fā)eg” resistors (i.e.,R1,k,wherek=0,1,…,n) with resistances ofβR0.

The current shunts at each nodeAk,so we get

whereis the equivalent resistance of the resistive network on the right side of nodeAk,which consists ofR1,k(k=0,1,…,n-1) andR2,k(k=0,1,…,n-1).It can be calculated as

Fig.2.Current-mode R-βR DAC:(a) schematic and its transfer functions:(b) no error,(c) analog-missing error,and(d) analog-overlapping error.

Substituting the resistor values and assuming thatk?1,(2) can be rewritten as

Solving (3) and substituting to (1) yields

In a conventional R-2R resistor ladder,whereβ=2,for eachkwe have

In this case,the currents are equally separated at each nodeAk,producing ideally radix-2 binary-weighted currents,i.e.,

whereI0is the least significant bit (LSB) current.Based on the digital input codeDin,the switches (i.e.,Sk,k=0,1,…,n-1) inFig.2(a) then direct the current branches to either the output node or the dummy ground.The output currentIoutcan be defined as

where,biis theith bit of the digital input code,andIiis the current of theith branch.When the digital code is also binary-weighted as in most cases,the output current is linearly proportional to the digital input,as shown inFig.2(b).

However,both discrete and on-chip fabricated resistors always suffer from component mismatches,resulting in a non-linear transfer function.To simplify the analysis,only one resistor value (i.e.,R2,n) will be changed.Considering the mid-code transition,i.e.,the digital input code increases from “0 1…11” to “10…00”,the output current will increase by

Their transfer functions are shown inFigs.2(b) to (d).Cases 2 and 3 both suffer from non-linearity problems,especially in high-resolution applications.For example,an 1% mismatch ofR2,nleads to 1.3-LSB and 326.0-LSB errors in the mid-code transition for 8-bit and 16-bit DACs,respectively.However,there are still some differences between them.InFig.2(c),there is a missing region in the analog domain,which means we cannot find any digital code to generate the analog output of this region.InFig.2(d),on the other hand,there is an overlapped region in the analog domain,which means we can use more than one digital code to generate the analog output of this region.In this case,it is possible to calibrate the transfer function according to the input code and bit-weight information.

In most cases,the resistances are normally distributed,so errors inFigs.2(c) and (d) occur randomly with equal probability.As discussed above,it is important to avoid the “analog-missing” error shown inFig.2(c).Therefore,we proposed a sub-radix-2 weighted resistor ladder with an intrinsic “analog-overlapping” error.It is implemented by simply changing the resistance ratio of R-βR DAC.According to (4),whenβ>2 and all resistor values are precise,for any mid-code transition from “xx…01…11” to “xx…10…00”,we can get an overlapped analog region as shownFig.2(d).The overlapped region becomes larger whenβincreases and varies due to the resistor mismatches.Therefore,we should choose aβvalue large enough to guarantee that no “analog-missing” error occurs for the worst matching case.

3.Digital Calibration Algorithm

Sub-radix-2 DAC proposed in Section 2 has an intrinsically non-linear transfer function,and it covers the full range of the analog domain.So,it can be corrected by adjusting the input code in the digital domain.The calibration algorithm pre-distorts the digital input codes according to the bit-weights of DACs,and the bit-weight is calculated automatically by an adaptive gradient descent algorithm.

Similar to (8),the output current ofn-bit sub-radix-2 DAC is

where Dcaland w are 1×nvectors representing the calibrated code for DAC and the actual bit-weight of DAC,respectively.The target of the pre-distortion algorithm is to find the best Dcalwhich minimizes the error between the output of sub-radix-2 DAC and ideal-linear DAC.Fig.3(a) depicts the procedure of the digital successive approximation register (DSAR) algorithm,which is inspired by the successive approximation register (SAR) analog-to-digital converter (ADC)[22].At the beginning of each converting cycle,the residue valueDris initially set to the digital input codeDin.The conversion starts from the most significant bit (MSB),whereDris compared with the MSB weightw[n].IfDr≥w[n],MSB is required in summing up the target analog value.Thus,MSB of Dcalis set to “1”,and the MSB weight is subtracted fromDr.Otherwise,MSB of Dcalis set to “0”,andDrremains unchanged.Then,the conversion steps forward to the lower bit until LSB.Afterncycles of the conversion,we get the calibrated code Dcalto make the output of DAC within an error of±1 LSB.

Fig.3.Flow charts of algorithms:(a) pre-distortion algorithm with DSAR and (b) adaptive bit-weights calibration algorithm with gradient descent.

There are several methods to get the actual value of each bit-weight,most of them need high-resolution ADCs.Fig.3(b) shows a low-cost alternative named adaptive bit-weight calibration (ABC).Firstly,two DACs’bit-weights w1and w2are initialized to the calculation values of ideal sub-radix-2 DAC without considering any mismatches.For each digital input codeDin(t),Dcal,1and Dcal,2are obtained with the DSAR algorithm based on two DACs’ bit-weights,respectively.Then,Dcal,1and Dcal,2drives two DACs to obtain the current outputsIout,1andIout,2.The bit-weights w1and w2are updated according to the comparison result ofIout,1andIout,2,and the changing step size is determined byΔ.The simple gradient descent methods will gradually reduce the output errors between two DACs.Once the two DACs are calibrated at different input codes,their transfer functions become linear and nearly identical.

Compared with previous works with high-resolution ADCs to measure the accurate transfer function of DAC,the ABC algorithm only needs two un-calibrated DACs and an analog comparator.Instead of calibrating each DAC to an ideal transfer function,the proposed method automatically adjusts the bit-weights to keep the transfer functions of two DACs being identical and linear.The algorithm can be further extended to high-density DAC arrays with a little modification.

4.Simulation Results

We use a behavior model to verify the proposed calibration method in MATLAB.Sub-radix-2 DACs are implemented by the R-βR resistor ladder,whereβ=2.1.For each resistor used in DACs,we assume a normally distributed mismatch with a 2% standard deviation.The update step sizeΔ,as shown inFig.3(b),of each bit is 1×10?6of the default bit-weight.A larger step size accelerates the calibration procedure but may cause converge problems and increase the calibration error.

We use two different digital input signals for the bit-weights calibration,an evenly-distributed random signal,and a sinusoidal signal with a frequency of 0.0001fs,wherefsis the sample rate of DAC.The amplitudes of both signals are from 10% to 90% of the maximum analog output range.Figs.4(a) and (b)show the output errors between two DACs in LSB.For both types of input signals,the inter-channel errors converge within 5.0×105iterations.The calibration procedure takes only 50 ms at a sample rate of 10 MHz,which can be easily implemented for on-chip R-2R DACs[9],[23].We also notice that the convergence is faster using the random signal input.Figs.4(c) and (d) show the calibrated MSB bit-weights.Almost simultaneously with the inter-channel errors,both DACs’ MSB bit-weights converge to their theoretical values.

Fig.4.Simulated calibration process of DACs:(a) and (b) the inter-channel output errors;(c) and (d) the calibrated MSB bit-weights of two DACs.The input signals for (a) and (c) are random signals and those for (b) and (d) are sinusoidal input signals.

The proposed method can also calibrate the gain errors between DACs.We add 5% gain errors with different polarities to DACs.Fig.5(a) shows the transfer functions of two un-calibrated DACs and ideal subradix-2 DAC without any mismatch,where the gains of both DAC channels are different from the ideal one.When DSAR is applied to pre-distort the input with the default bit-weight,the linearity is greatly improved as shown inFig.5(b).The gain and the mid-code transition error,however,remain large.It is also worth noticing that the digital input code range reduces by 20%,which is caused by removing the overlapped region in the transfer functions.After 5.0×105cycles of adaptive calibration,the bit-weights are learned automatically.InFig.5(c),there is nearly no gain error between DACs.

Fig.5.Transfer functions with different calibration methods:(a) without DSAR,(b) DSAR with default weight,and(c) DSAR with calibrated weight;the inter-channel errors of DACs with different calibration methods:(d) without DSAR,(e) DSAR with default weight,and (f) DSAR with calibrated weight.

Figs.5(d) to (f) show the normalized inter-channel error,which is defined as the difference between the analog output of DACs.If the DACs’ gain matches perfectly,the inter-channel error will be around zero.Figs.5(d) and (e) show that the un-calibrated gain error between DACs is about 10%,and the default bit-weights calibration with DSAR enlarges the gain error as the input range becomes smaller.However,the proposed algorithm restores two linear DACs with the channel error less than ±20 ppm,which is around±1.3 LSB for ideal 16-bit binary-weighted DAC.

Differential nonlinearity (DNL) is the difference between the actual and the ideal step sizes corresponding to DAC’s outputs with two consecutive input codes.Integral nonlinearity (INL) is the difference between the ideally linear-fitted curve and the actual curve of DAC’s transfer function.They are both vital indicators that measure the static performance of DAC.Figs.6(a) and (d) show DNL and INL of two uncalibrated DACs,respectively,both are poor with over 100-LSB absolute errors.However,uncalibrated DNL of sub-radix-2 DACs is always less than 1 LSB,which means no analog-missing error occurs.Figs.6(b) and (e) show DNL and INL with DSAR using the default bit-weight,respectively.DSAR calibrates the intrinsic non-linearity of sub-radix-2 DACs,and improves both DNL and INL.DSAR calibrates the intrinsic non-linearity of sub-radix-2 DACs,and improves both DNL and INL.However,random mismatch errors become predominant.This also appears in conventional binary-weighted R-2R DACs,and limits the high-resolution applications.Figs.6(c)and (f) show DNL and INL with DSAR using the calibrated bit-weight,respectively.DNLs of both channels are within ±1 LSB,and INLs are with ±0.5 LSB.As shown in the figures,the ABC algorithm together with the DSAR pre-distortion significantly improves DNL and INL,despite using low-accuracy components.The simulation results prove that sub-radix-2 DAC based on the R-βR resistor ladder can be used in high-resolution applications with digital calibration.

Fig.6.DNL of DACs with different calibration methods:(a) without DSAR,(b) DSAR with default weight,and (c) DSAR with calibrated weight;INL of DACs with different calibration methods:(d) without DSAR,(e) DSAR with default weight,and (f) DSAR with calibrated weight.

The conventional DAC calibration method needs to measure the bit-weight mismatches and store the calibration values before usage.During the operation mode,DAC’s calibration values are fixed.However,the bit-weights of DAC sometimes change with time.For example,resistors fabricated on-chip usually have poor temperature stability.Temperature gradients may affect the resistance values of DACs located in different parts differently.In this case,continuous background calibration is in great demand.The ABC algorithm,as a digital calibration method,can continuously calibrate the bit-weights and track their changes over time.The proposed calibration method can work in the background.

Fig.7shows the spectrograms of two 16-bit sub-radix-2 DACs,when the background calibration process is performed.The input signal is a continuous sinusoidal wave with an amplitude covering 10% to 90% of the maximum signal range.Initially,the bit-weights are set to the default value,and each channel has a poor signal-to-noise-and-distortion ratio (SNDR) of around 42 dB,i.e.,7-bit effective number of bits (ENOB).The ABC algorithm achieves a significant improvement in linearity in 1.2×105iterations,when SNDR increases to around 87 dB,i.e.14.5-bit ENOB.SNDR and ENOB are improved by 45 dB and 7.5 bit,respectively.Then the bit-weight of channel 1 (CH 1) changes rapidly by 1% (iteration=2.0×105).SNDR of CH 1 reduces to 53.0 dB,and the calibration restarts to rematch the outputs of two DACs.SNDR of channel 2 (CH 2) also reduces to 58.6 dB,because the calibration algorithm cannot identify which channel is changed and needs to re-calibrate both channels.And 5.0×104cycles later,the DAC outputs are correctly calibrated again,resulting in 87-dB SNDR.Then we apply the bit-weight changes to CH 2 (iteration=4.0×105) and both channels(iteration=6.0×105),for both cases the proposed background calibration algorithm can finally correct the analog output signals.

Fig.7.Spectrograms of the outputs of two DACs with background calibration.

The simulation results above verify the effectiveness of the proposed DSAR pre-distortion and ABC algorithm.They can be easily integrated into embedded systems and integrated circuits (ICs),as there are no complex calculation operations,such as multiplication and division.Although the previous analyses and simulations are based on a 2-channel example,the proposed calibration method can also be generalized to more channels.Consider a DAC array withM(1 ,2,…,M) channels,where channeliand channeli+1 are calibrated by the proposed method (0

Table 1:Performance summary and comparison with previous works

5.Conclusion

This paper proposed a low-costin situcalibration method for high-resolution resistor ladder DAC.The proposed sub-radix-2 DAC is implemented with the R-βR resistor ladder.We proposed a low-cost method for calibrating both non-linear transfer functions and the inter-channel mismatches between two DACs based on the digital successive approximation register and the adaptive bit-weight calibration algorithms.In addition,the behavior model simulation results show that both the static and dynamic performance of the proposed DACs are significantly improved.Besides,the proposed method can operate in the background and continuously track and correct any error caused by bit-weights variations.By taking full advantage of the digital processing capacities brought by modern sub-micron IC processes,high-resolution DACs will become smaller and smarter.

Acknowledgement

This work is also sponsored by “Shuguang Program” supported by Shanghai Education Development Foundation and Shanghai Municipal Education Commission,and the Fundamental Research Funds for the Central Universities.

Disclosures

The authors declare no conflicts of interest.