Ali Hussien Majeed | Mohd Shamian Zainal | Esam Alkaldy | Danial Md.Nor

Abstract—To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor (CMOS) technology developers.The scaling scenario is not an option nowadays and other technologies need to be investigated.The quantum-dot cellular automata (QCA)technology is one of the important emerging nanotechnologies that have attracted much researchers’ attention in recent years.This technology has many interesting features,such as high speed,low power consumption,and small size.These features make it an appropriate alternative to the CMOS technique.This paper suggests three novel structures of XNOR gates in the QCA technology.The presented structures do not follow the conventional approaches to the logic gates design but depend on the inherent capabilities of the new technology.The proposed structures are used as the main building blocks for a single-bit comparator.The resulted circuits are simulated for the verification purpose and then compared with existing counterparts in the literature.The comparison results are encouraging to append the proposed structures to the library of QCA gates.

1.lntroduction

The complementary metal oxide semiconductor (CMOS) technique has many drawbacks,such as high lithography,short channel effect,and high power consumption,so it cannot continue following the Morrie’s law in increasing the number of devices per single chip.All these drawbacks prompted scientists to think about alternative technologies that have the ability to work in nanoscales,such as the single electron transistor (SET)[1],[2],carbon nanotube field effect transistor (CNFET)[3],fin field effect transistor (FinFET)[4],[5],and quantum-dot cellular automata (QCA).QCA was introduced for the first time by Lentet al.[6].QCA can provide binary values by the electron position instead of the voltage level as that in CMOS.The primitive element in QCA is a square cell.Each cell contains four dots injected by two electrons.Electrons can tunnel between dots depending on the principle of electron repulsion.The circuit complexity is an important standard in digital systems,especially in QCA.Many combinational and sequential circuits have been re-designed with the QCA technology[7]-[13].Given the importance of the comparator in the microcontroller and central processing unit (CPU),therefore,different QCA structures were proposed[14]-[18].

This paper presents an optimized design of a single-bit comparator using the QCA technology based on novel XNOR structures.The QCADesigner tool[19]is used with the default parameters of the simulation environment to verify the proposed structures and circuits.

2.Preliminaries

2.1.QCA Basics

The QCA cell is the fundamental unit in a QCA based design.Each cell,square-shaped,contains four quantum dots injected with two electrons.These two electrons can move between dots and settle in a diagonal position because of the Columbic interaction and depending on the driver cell[16],[20].The two arrangements of the cell are illustrated inFig.1.The cell polarization (P) represents binary 1 atP=+1 and binary 0 atP=–1,which is calculated from (1)[21]:

Fig.1.Cell polarization.

wherepirepresents the existing of the electron in the doti,either 0 or 1.Note that when the dot has an electronp=1,elsewherep=0.All logic functions and the QCA wire can be performed by arranging an array of cells[22].

2.2.QCA Wire

To carry the input value to the output,the QCA wire is required and comprised of QCA cells.Due to the Columbic interaction between electrons,the polarization transfers from one cell to another[23].The QCA wire has two configurations,normal and rotated,as shown inFig.2to achieve wire crossing in the same circuit layer.Single layer wire crossing is done by clocking control,which is the same as that in [24].

Fig.2.QCA wire:(a) normal and (b) rotated.

2.3.QCA Gates

The universal gate in QCA is the majority gate.The basic logic gates,AND and OR,can be implemented using this gate by applying one of the inputs to 0 or 1,respectively,which have been focused on by several published papers[25]-[27].Two forms of the majority gate have been presented in QCA,as shown inFig.3[28],[29].The general formula of this gate is given by

whereMdenotes the majority of three digital inputsA,B,andC.

Generally,the majority gate with an inverter represents a basic building block in QCA circuits.There are three configurations of inverters in QCA,as illustrated inFig.4.The structures inFigs.4 (a)and(c)are not robust like the structure inFig.4 (b).

Fig.3.QCA-majority gate:(a) normal form and (b) rotated form.

Fig.4.QCA configurations of inverters in QCA:(a) corner form,(b) reliable form,and (c) rotated form.

2.4.QCA Clocking

To do the computation and to ensure the data direction flow toward the output,QCA clocking is used.Clocking is also essential to provide the power for the QCA circuit and to control the data flow direction[16],[30].The clock controls the barrier between dots.When the clock is low,the cell polarization remains unclear.The cell gets its fixed polarization when the clock is high.The clock signal is comprised of four clock phases,to ensure adiabatic cell switching,including switch,hold,release,and relax.The QCA circuit can be divided into 4 clock zones where each zone contains four phases as illustrated inFig.5[31].

Fig.5.Clock signal in four zones.

3.Single-Bit Comparator

Fig.6.Logic diagram of single-bit comparator[32].

In the logic design,the comparator is an important component.It can distinguish three states of two numbers:Equal,greater,or less[16].Fig.6shows the block diagram of the single-bit comparator circuit,where–1 represents logic 0[32].The circuit receives two signalsAandB.The upper majority gate gives high (logic 1) whenA＜B.IfA＞B,the lower majority gate gives high at the output.The XNOR gate gives high only if both two signals are high.Table 1explains the response of three gates used inFig.6to all input states.

Table 1:Single-bit comparator truth table

4.Related Work

QCA comparator circuits have been introduced earlier by many researchers.In [14],a QCA comparator circuit was designed in a multi-layer structure with an area of 0.06 μm2and 73 cells,as shown inFig.7.In [18],the authors proposed a single-bit comparator.This QCA comparator circuit needs a multi-layer structure for implementation with an area of 0.04 μm2and 54 QCA cells as illustrated inFig.8.In [33],a competitive area and cells count comparator circuit was proposed.As shown inFig.9,this QCA comparator circuit suffers from the inefficient output because the output of XNOR takes from the corner inverter directly,where this often needs extra cells before the output cell,to be stable,and if any additional cell is put before the output cell,the whole circuit will be changed.

Fig.7.Single-bit comparator proposed in [14].

Fig.8.Single-bit comparator proposed in [18].

Fig.9.Single-bit comparator proposed in [33].

5.Proposed XOR and XNOR Structures

In this paper,two structures of the QCA-XNOR gate (XNOR-1 and XNOR-2) are proposed as shown inFig.10.Further,this paper presents a novel structure of a 3-inputs XOR gate.From this gate,an optimal form of the XNOR gate can be derived as illustrated inFig.11.The proposed structures come from the inherent capabilities of QCA and do not follow any combinational function.These three structures will be used for designing the single-bit comparator.All the proposed XNOR gates are single-layer gates,which have a good distance between inputs to avoid the crosstalk effect.And the output cells are in the outer part of the gate.The first and second structures (XNOR-1 and XNOR-2) are designed directly as the XNOR gate,while the third one (XNOR-3) is the XOR gate with an inverter.

Fig.10.Proposed QCA structures:(a) XNOR-1 and (b) XNOR-2.

Fig.11.Proposed structures:(a) 3-inputs XOR gate,(b) 2-inputs XOR gate,and (c) XNOR-3.

6.Comparator lmplementation

Depending on the proposed gates,a single-bit comparator can be implemented,as shown inFig.12,following the block diagram given inFig.6.The first proposed XNOR gate is used inFig.12 (a)to build the comparator circuit to compare between two single-bit inputs (AandB) with three outputs.XNOR-2 and XNOR-3 are used inFigs.12 (b)and(c),respectively,to design the single-bit comparator.All the proposed designs have two majority voters and differ by the structure of the XNOR gate.

Fig.12.Proposed single-bit comparators by using:(a) XNOR-1,(b) XNOR-2,and (c) XNOR-3.

7.Simulation Results

The output waveforms of the proposed XNOR-1,XNOR-2,and XNOR-3 gates are shown inFigs.13 (a),(b),and(c),respectively.The inputA,B,andCsignals for the proposed 3-inputs XOR gate and the output signal are shown inFig.13 (d),while the red signal represents the clock signal to the circuit.InFig.13 (e),the two input signals and the output signal of the derived 2-inputs XOR gate are shown.It is clear from the figures that all the proposed gates have an error-free operation.The simulated output waveforms of the comparator circuits are illustrated inFig.14.Two single-bit signals (AandB) are fed to the proposed comparators and it is obvious that,in each proposed circuit,the proper result is obtained in the three outputs of the circuit in each case.

Fig.13.Simulated output waveforms of the proposed gates:(a) XNOR-1,(b) XNOR-2,(c) XNOR-3,(d) 3-inputs XOR,and(e) 2-inputs XOR.

Fig.14.Simulated output waveforms of the proposed circuits:(a) comparator with XNOR-1,(b) comparator with XNOR-2,and (c) comparator with XNOR-3.

8.Comparison

The proposed XNOR and XOR gates are compared with the previously reported designs and the results are shown inTable 2[20],[21],[24],[34]-[38].It is clear that the proposed gates are competitive with the best published designs.Another important advantage for the proposed gates is the proper distance between the input cells,which will give the required freedom to design more efficient circuits.Another metric in the QCA circuit called the cost function has been considered in this work.This metric can be calculated,according to [39],by multiplying the three main metrics including complexity,area,and delay.

Table 2:Proposed gate comparison

The proposed single-bit comparator circuits have been compared with earlier presented designs and the results are presented inTable 3[14],[17],[18],[33],[40]-[45].It can be easily observed that the proposed designs have a noticed preference in terms of the number of required cells,which determines the circuit complexity.In addition,the proposed designs are retaining the minimum area and latency.

Table 3:Single-bit comparator comparison results

9.Conclusion

This paper presented two novel structures of XNOR gates (XNOR-1 and XNOR-2) and a new structure for 3-inputs XOR implemented by the QCA technology.Adding an inverter to the proposed 3-inputs XOR,a new 2-inputs XNOR gate (XNOR-3) was derived.The comparator implementation depending on the new gate has been investigated and the results show an about 8% reduction in complexity (the number of cells needed) for the proposed comparator with XNOR-2 and 13% for the proposed one with XNOR-3.Additionally,the proposed gates can be considered as a new addition to the QCA building block library to enrich the design methodology with this technology.

Disclosures

The authors declare no conflicts of interest.