LIU Bojiang()， YAN Ran( )， CHAI Haiyan()， HAN Xinyu()， TANG Longli()

China Shipbuilding Software Quality&Reliability Testing Center，Beijing100081，China

Abstract：In order to solve the current high failure rate of warship equipment field programmable gate array(FPGA)software，fault detection is not timely enough and FPGA detection equipment is expensive and so on.After in-depth research，this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment(ISE)and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA，this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis.This test method has important engineering significance for the upgrading of warship equipment.

Key words：Field Programmable Gate Array(FPGA)；fault；prediction；diagnosis

Introduction

With the widespread use of field programmable gate array (FPGA) technology in warship equipment， there is an increasing need for a method that can test the functionality and timing accuracy of FPGA software. At present， although many large companies abroad have produced some high-end functions and timing tools that can implement the test verification function of FPGA circuits， such devices are expensive. Therefore， it is necessary to study a method for verifying the function and timing accuracy of FPGA software.

With the increasing application of FPGA in the ship field， its reliability becomes more and more prominent， and the fault prediction and diagnosis of electronic components become more and more important， so the demand for FPGA fault prediction and diagnosis becomes more and more important.

(1) FPGA overview

The emergence of FPGAs has greatly reduced the cycle and cost of electronic product research and development(R&D). Due to its advantages of high speed， high reliability， and low power consumption， FPGAs have acquired a large number of fields in aviation， aerospace， and shipping application[1].

(2) ModelSim overview

ModelSim is an hardware description lamguage(HDL) simulation tool that we can use to implement a stand-alone or mixed simulation of a designed very-high-speed integrated circuit hardware desciption language(VHDL) or Verilog program. This article uses ModelSim SE10.1a for HDL simulation.

(3) Xinlinx ISE Introduction

This article uses Xilinx ISE version 14.7， which comes with timing analysis tools， but the actual use of the effect is not as good as ModelSim software， so this article uses Xinlinx ISE as an integrated development environment to test FPGA software to write timing constraints.

(4) Xinlinx ISE and ModelSim combined simulation

Using ModelSim and Xinlinx ISE to co-simulate the HDLs used by the FPGA requires the compilation of Xinlinx libraries， including unisim， simprim， xilinxcorelib， aim， pls， cpld，etc. With these library files， we can generate behavioral simulations of the design in Xinlinx ISE.， post-conversion simulation， post-mapping simulation， post-placement simulation of various models， and then in the ModelSim simulation of these models， because Xinlinx ISE and ModelSim has achieved a seamless connection， only need to set a visible in Xinlinx ISE Waveform files， and then a few clicks to achieve a variety of simulations.

1 FPGA System Features

1.1 Difference between FPGA system and software system

As a programmable logic device， FPGA make the universal chip into a user-needed hardware digital circuit through a programming method (such as HDL). FPGA and software system have similar structures and development methods. HDL and software are the products of human brain thinking logic[2]. has a similar syntax and failure mechanism. Therefore， using the mature technology of software testing for FPGA testing is feasible both in theory and operation.

However， because of the different nature of software and hardware systems， FPGAs and software systems have some differences in test requirements. Table 1 shows the development methods， code execution sequence， hardware impact， randomness of application results， and application areas.The difference between FPGA and software system is summarized.

Table 1 Comparison of FPGA system and software system

1.2 Test level requirements

Unlike traditional bottom-up electronics design techniques， FPGAs use the same top-down design approach as software development. The development process of a project， from the decomposition of the system， the establishment of the RTL model， the generation of the gate-level model， to the final underlying circuit that can be physically wired， is a development cycle from a high abstraction level to a low abstraction level.

In the development process， simulations such as behavior simulation， functional simulation， and gate-level timing simulation are required to be performed at each stage. In the testing stage， testing from the gate level， component functional level， and system behavior level is required from the bottom up.

1.3 Test level

For the differences between FPGAs and software systems， there are different testing requirements unique to software testing， including HDL code testing requirements， test level requirements， and timing test case design requirements.

The process of combining abstract entities into a single entity or a unified entity is called synthesis. Each step of the development process of an FPGA system can be called an integrated link. That is， the natural language representation is converted into a HDL algorithm through natural language synthesis， and then it is converted through comprehensive behavior. At the register transfer level (RTL)， it is further converted into a logic gate representation through logic synthesis， and finally converted into a layout representation through structural synthesis. For each comprehensive link， corresponding to the corresponding test level， FPGA test “V” model is shown in Fig. 1.

Fig. 1 FPGA test “V” model

With software testing， testing plays a role of verification and validation during the FPGA development phase. The difference is that the output of each comprehensive link of the FPGA is a formalized representation of the design. It can not only be verified through static methods， but also has a powerful simulation tool to support the dynamic simulation of each integrated link during the development phase. Verification， this is more conducive to early detection of defects and reduce the cost of FPGA software development.

2 Test Methods

The FPGA testing method proposed in this paper adopts the open-loop design mode and the idea of black box testing， simulates and observes the external signal characteristics of the tested FPGA， and completes its testing.

The overall design architecture is that the tester edits the signal, then the single needed to be verified by the waveform editor deployed on the host computer， and the test vector of the signal that was successfully edited generates the test vector. The master FPGA chip of the test board is generated by generating the command control function. General-purpose module FPGA， output gated FPGA and the entire test process control the main FPGA.

2.1 Functional simulation

Functional simulation is the most important of all simulation types， and it is also the simulation that accounts for the largest proportion of project development and testing. It is necessary for any project.

2.1.1Serialsimulationparallelthinkinganalysis

Simulation principle is an important part of FPGA project development. It is an important method to ensure that the HDL design code is functionally accurate. The circuits in the FPGA are executed concurrently， so the nature of the HDL language is also parallel， and the hardware circuit is always working[3].

Serial emulation parallelism is mainly divided into two situations： independent parallel circuits and associated parallel circuits.

(1) Independent parallel circuits

If parallel circuits are independent of each other， then at the same time[4]， starting N things at the same time and doing one thing and then starting the next thing are exactly the same from the result. For example， the inputs of the adder 1 are A and B， the output is C， the inputs of the adder 2 are D， E， and the output is F， as shown in Fig. 2.

Fig. 2 Independent parallel circuits

(2) Parallel parallel circuits

If the parallel circuits are not mutually independent， for example， the inputs of the adder 1 are A and B， the output is C， the inputs of the adder 2 are C， D， and the output is E， as shown in Fig. 3.

Fig. 3 Parallel parallel circuits

At this point， whether you are looking for two people at the same time to calculate the output of two adders or only find one person to calculate the output of two adders one by one in any order， the final answer will be the same[5]. Therefore， serialization in this case can be easily simulated in parallel.

2.1.2.Combinationallogicsimulationprinciple

The principle of combinatorial logic simulation is based on the above analysis， and this is called “serialization and serialization.” Therefore， it is necessary to pay attention to a reasonable statement sequence arrangement to achieve a correct and efficient combinational logic function simulation[6].

2.1.3Timinglogicsimulationprinciple

The most important thing in the sequential logic is the register. Taking a most basic rising edge-sensitive register as an example， it has three important ports， namely two input portsclk， D， and an output port Q. Its function can be described as： no matter how the value of the input port D changes， if and only if the rise of the clk arrives， the value of the update output port Q is the value of the input port D at that time. After that， the value of port Q will remain until the next arrival of the rising edge of clock is possible to update.

2.2 Simulation syntax

2.2.1Graphicwaveform

The graphic waveform method is fundamental to functional simulation and must be mastered by FPGA testers.

Graphical waveforms are graphical representations of logic levels versus time. In the FPGA design， binary logic levels are used， and for the sake of consistency， logic 1 and logic 0 are used to represent differences in logic levels.

When using the graphic waveform method to simulate the FPGA design， the input of the simulation waveform is generally tool-dependent because different simulation tools provide different waveform formats， rendering methods， and simulation interfaces. The general steps are as follows：

Step 1 Preparatory work.

Step 2 Add the input port and the output port to be observed in the waveform.

Step 3 Draw input excitation waveform diagram.

Step 4 Observe the waveform of the output port and perform simulation analysis accordingly.

2.2.2VHDLtestbench

This method requires high VHDL syntax and requires testers to master the VHDL design description syntax[7].

2.2.3SystemVerilog

System Verilog， abbreviated SV， is a very powerful language. It is based on the Verilog language. It inherits all Verilog syntax. It is a hardware verification language.

2.2.4Assertion

Assertion is a debugging method commonly used in programming languages. It is a tool for FPGA simulation. Assertions are divided into immediate assertions and concurrentassertions[8]. Immediate assertions are actually a simplified if conditional statement that can occur where any serial statement can appear； concurrency assertions are like a sequence always， with a certain clock edge Trigger events and periodically monitor the simulation.

2.3 Timing analysis

Timing analysis is also called static timing analysis. It mainly concludes from the FPGA design implementation point of view， and see if the desired logic function can be implemented by a specific FPGA chip under the current process conditions. Like functional simulation， timing analysis is a must for any project.

For FPGA design， after obtaining its corresponding various time parameters and time delays， the corresponding static timing analysis tools can be used for timinganalysis[9].

3 Example Applications

Take an FPGA project with DCM and FIFO as an example to introduce how to use Xilinx’s Verilog simulation library to complete the simulation in theModelSim environment.

The design to be simulated is as follows.

module top V(

inputclk，

inputsrst，

input[7：0] din，

inputwr_en，

inputrd_en，

output[7：0]dout，

output clk2x

)；

tfifo YourInstanceName(

.clk(clk)，

.srst(srst)，

.din(din)，

.wr_en(wr_en)，

.rd_en(rd_en)，

.dout(dout)，

)；

mydcm instance_name(

.CLKIN_IN(clk)，

.RST_IN(srst)，

.CLK2X_OUT(clk2x)

)；

.

.

.//and so on

endmodule

Writing test motivation using Verilog is as follows：

modulettv；

//inputs

reg clk；

reg srst；

reg[7：0] din；

reg wr_en；

reg rd_en；

//outputs

wire[7：0]dout；

wire clk2x；

endmodule

Fig. 4 FPGA test waveform

Fig. 5 Pa Simulation debug circuit

Through Figs. 4-5 the waveform graph can clearly show the high and low level display of each signal， thus quickly find the fault in the FPGA software， simulation debug circuit can display the FPGA electrical connection form.

4 Conclusions

This paper studies the fault detection theory of warship equipment FPGA， explores the FPGA fault prediction and diagnosis method， uses Xinlinx ISE and ModelSim software to carry out functional simulation of the warship equipment FPGA software， and explores the fault detection to achieve high fault coverage and improved fault detection efficiency have important engineering implications.