ZHANG Xuejiao, CUI Keji, ZHENG Lirong

(School of Information Science and Technology, Fudan University, Shanghai 201203, China)

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A Resolution Tunable Coarse-Fine Time-to-Digital Converter Used in ADPLL

ZHANG Xuejiao, CUI Keji, ZHENG Lirong

(School of Information Science and Technology, Fudan University, Shanghai 201203, China)

This paper presents a design of a coarse-fine time-to-digital converter (TDC) for all-digital phase-lock loop (ADPLL). The first stage is based on a buffer delay-line chain. A sense-amplifier flip-flop (SAFF) with asynchronous reset is used as the sampling elements. Then the input signal and its adjacent reference clock are injected into a vernier-delay-line (VDL) time-quantizer at the second stage, achieving a finer resolution. The proposed architecture can provide high resolution with less hardware compared to the one-stage VDL TDC with the same dynamic range. A delay-tunable buffer is utilized to tolerate the process, voltage and temperature (PVT) variations. The design has been verified in a 65nm CMOS process with the area of 0.06mm2. The simulation results show that the time resolution is up to 6.15ps with the input frequency of 1.2—1.8GHz. The power consumption is less than 2.5mW and the dynamic range is 1260ps corresponding to 8bits resolution.

time-to-digital converter; coarse-fine architecture; Vernier delay line; tunable resolution

A time-to-digital converter (TDC) is used to quantize the time interval between the rising edges of two signals. Recently, it has become increasingly popular in mainstream micro-electronics, especially in mixed-signal systems such as all-digital PLLs[1]and time-domain ADCs[2-3]. The TDC replaces the phase detector (PD) and serves as a key building block in an all-digital PLL. Its main function is to measure the time interval between the rising edges of high-speed digital-controlled-oscillator (DCO) output and low-speed reference clock.

Compared to an analog PLL, an ADPLL can be realized by very small and simple circuits, resulting in programmability and robustness. However, the TDC creates quantization noise, increasing the loop’s in-band phase noise. Choosing a proper architecture of TDC is important to improve the performance of the ADPLLs.

In this paper, we propose a two-stage conversion scheme combing a coarse quantizer and a fine quantizer, which can provide a wide dynamic range and a fine time resolution with low power consumption and small chip area. The first stage is based on a buffer delay-line chain, achieving 1260ps dynamic range. Then a resolution up to 6.15ps is realized by the second stage. The whole power consumption is less than 2.5mW. This TDC is verified in a 65nm CMOS process.

1　Theory analysis of TDC

1.1Function analysis

Generally, a TDC quantizes their time difference of two asynchronous input signals. That means the time interval can be represented solely upon the output thermometer code. However, the application of TDC in the ADPLL is quite different. In ADPLLs, we don’t care about the specific value of one time interval, but pay attention to the frequency ratio between the DCO output and the reference clock. Thus it is necessary to compare the time interval with the DCO period to get the fractional frequency division ratio. Observe the Fig.1, the factional division ratio can be calculated as

(1)

where thetCKVis the quantized period of the DCO output, Δtis the quantized time interval between two rising edge of the reference clock and the DCO output[4]. Then the scaling factorεcan be used to update the frequency-control-words (FCW) to control the output frequency of the DCO, as Fig.1 shows.

1.2Characteristic analysis

The performance of TDCs is characterized by a number of parameters, among them, resolution, precision, linearity, voltage and temperature sensitivities, conversion time and dynamic range are important.

Designed for ADPLL which is applied to GSNN system, the TDC should cover the operating frequency, which means its dynamic range should cover the ADPLL’s maximum period.

On the other hand, the in-band phase noise of an ADPLL is strongly affected by the time resolution of the TDC, expressed as

(2)

wheretCKVis the quantized period of DCO output,fREFis the frequency of the reference clock, andtresis the time resolution determined by the delay of the buffer chain[4]. Provided that the required in-band phase noise is around -105dBc/Hz for 1.2-1.8GHz systems, a time resolution less than 10.9ps is needed which is derived by substitutingfREF=40MHz into formula (2). However, a conventional TDC cannot achieve sub-10ps time resolution due to the restriction of nano-scale CMOS technology.

The non-linearity of a TDC is the deviation of the time-to-digital transfer characteristic of the TDC from that of an ideal TDC. In reality, non-linearity lowers the time resolution together with clock jitter, worsening TDC performance. For delay-line TDCs, non-linearity is caused by the difference between the delays of buffer stages arising from PVT variation. That’s why it is important to decrease the influence of PVT variation.

1.3TDC architecture comparison

Generally, the TDC has two key specifications, dynamic range which must cover at least one period of the DCO, and time resolution which should be as fine as it can be.

The traditional TDC is based on digital delay elements which, unfortunately,suffer from PVT variations. The delay-locked-loop (DLL) regulated TDC can provide accurate delay that is proportional to the input signal period. However, there is a limitation on the minimum resolution due to the dynamic range. At the same resolution, the dynamic range is in proportional to the number of buffer stages. Unfortunately, large numbers of buffer stages generally decrease the linearity of the TDC, and this would reduce the effective resolution of the TDC. For instance, the DLL TDC only achieves 16 ps resolution under a reference clock generated by crystal[5]. Similarly, the TDC for sub-gate delay resolution also suffers from the same problem, such as the parallel TDC, the Vernier TDC[6]. For example, the TDC based on parallel scaled delay elements can achieve a 3ps resolution but some problems like drivers and skews are challenging especially for a high dynamic range[7]. Recent advances in achieving high resolution of TDC propose the use of Time Amplifiers (TAs)[8-10]. The TA amplifies a small time difference to a larger time difference, improving the resolution, even up to 1.12ps[10]. Nevertheless, the TA suffers from inaccurate gain and insufficient input linear range and thus complex calibration is required.

To solve the contradiction between the dynamic range and the minimum resolution, we propose a two-stage conversion scheme. It consists of a coarse quantizer, an edge detector and a fine quantizer. This structure can provide a wide dynamic range and a fine time resolution without extra power and area. To decrease the power consumption, a power-saving circuit is introduced in the front end. In addition, a calibration circuitry is employed to calibrate the two-stage’s resolutions.

2　Design of two-stage TDC

2.1Coarse quantizer

The coarse quantizer uses the buffer chain to delay the reference signal (Fig.2). To achieve sufficient dynamic range, the total delay time of the buffer chain should cover at least one DCO period. The dynamic range and the number of the buffer stages determine the coarse time resolution of the 1st-stage time quantizer.

Because the frequency of DCO output is dozens of times that of the reference clock, an amount of power is dissipated. As shown in Fig.2, a power-saving circuit is adopted in stage TDC, achieving >50% power saving[1]. This circuit is simply composed by two logic gate and a flip-flop. The XOR gate generates a time-window signal from the input reference and the final output of the delay chain. Then, the time-window signal is sampled by the DCO output, to remove the useless periodic signal, as shown in Fig.3.

2.2Edge detector

An edge detector in Fig.4, identifies the delayed REF whose rising edge is close behind the DCO rising edge. The outputs of the flip-flops are propagated to the edge detector. Because of asynchronous trigger, the low-order output changes ahead of the high-order one. To ensure that both low-order output and high-order output arrive at the NOR gate at the same time, a set of parallel delay buffers are inserted. Then an OR operation combines the outputs of what into the REF_D and sends it to the 2nd-stage quantizer. As shown in Fig.3, the flip-flop outputs start with “0” and the eighth bit changes from “0” to “1” when its reference clock comes. The jumping signal goes through the edge detector and finally turns into the REF_D.

Those previous analyses happen in the ideal situation, but in fact, there are many non-ideal conditions. The first one is that the real REF_D occurs after the ideal one because of the path delay. Therefore, the output of DCO must go through the same path to make sure the time interval unchanged. Secondly, the last quantization results may interfere with the new ones. For example, provided that two sequential outputs of the flip-flops are “11” after the last quantization but now are “00” in the new quantization (low in the first), the low-order bit changes before the high-order one, so the outputs will first change to “01” then to “00”, resulting in a wrong jumping signal. Hence, to avoid those errors, the sense-amplifier flip-flop (SAFF) adds an asynchronous reset port which is enabled by the reference falling edge (Fig.5).

2.3Fine quantizer

The obtained step signal，CKV_D and REF_D are injected to the second stage to digitize further more (Fig.6, see page 170). After the coarse quantizer, the time interval between CKV_D and REF_D is smaller than the coarse resolution. So the fine quantizer adopts a Vernier-delay-line chain with two buffer-delay-line chains, in order to get the fine resolution. The difference between the propagation delays of the buffer delay chains (tbuf2andtbuf3) can create a much smaller resolution than the smallest single gate delay in recent technology.

However in reality, the buffer delay is unstable due to the effect of PVT variations. To reduce the PVT’s influence on the time resolution, the TDC employs a buffer whose delay is controlled by voltage. With the control port, it is easy to change the buffer delay, keeping the minimum resolution. This method is also implemented in the first stage to ensure the dynamic range.

To align the coarse/fine codes, the ratio of coarse versus fine resolution should be calculated. A calibration circuit creates two signals BUF1_1 and BUF1_2, whose time difference is the same as the propagation delay of BUF1(tbuf1). Then the time difference is measured by the 2nd-stage quantizer when the REF is low. So the obtained calibration factor is expressed as

(3)

As a result, the fractional phaseεis calculated as

(4)

whereBDtandBdtare the digitized time difference of two stages,BTCKVis the digitized period of DCO output, respectively,Kresis the calibration factor.

3　Simulation results

The TDC circuits are implemented in a 1.2-V 65-nm mixed signals CMOS technology.

The code versus actual time interval plot is presented in Fig.7 by simulation which illustrates the linearity of the TDC. It can be observed that the overall trend of the TDC is linear with the input frequency of 1.2—1.8GHz. But there are some depressions in the ladder curve. The cause of this phenomenon is the mismatch between the adjacent buffers. So when the time interval is approaching an integral multiple of coarse TDC’s resolution, the deviation of for-and-aft buffers’ delays would introduce errors here. Moreover, the flip-flop’s limited set-up time is the other reason. This also can be seen in the INL and DNL plot (Fig.8). Using the flip-flop whose set-up time is insensitive to the time interval between inputs can optimize the linearity.

The effect of PVT variations is estimated using a pre-layout simulation (Fig.9). The simulation settings of the process, temperature and supply voltage are fast corner, -40℃ and 1.3V for the fast condition, and sow corner, 80℃ and 1.1V for the slow condition. It can be seen the variation of the time resolution is only 4ps between fast and slow PVT condition. As shown in Fig.9, in the fast condition, the time resolution becomes better, but the dynamic range can’t satisfy the system’s requirement. With the control voltage, the dynamic range in the fast condition can be improved to 1250ps.

The performance of the proposed TDC is summarized in Tab.1 with prior published TDCs. The BB DLL used in Ref.[5] can improve the linearity of TDC. However, both its resolution and power dissipation are very bad. Although TA pipeline TDC[10]can achieve the best resolution of all, TA’s nonlinearity introduce narrow dynamic range. Moreover, the complexities of TA’s circuits and pipeline architecture result in large power and area consumption. The Vernier TDC[11-12]also improve the resolution of TDC, better than single inverter delay. Paradoxically, wider dynamic range in Vernier TDC means longer chain of buffers, longer chain means larger mismatch of buffers, causing worse linearity. Using GRO technique can solve this problem, but it doesn’t apply to ADPLL for that it couldn’t calculate the period of ADPLL output. Compared with previous works, the proposed TDC achieves fine time resolution and enough dynamic range for GPS system.

Tab.1　The summary and comparison of TDC performance

4　Conclusion

In this paper, a coarse-fine TDC implemented in 65nm technology is presented. By employing the technique of multi-level and VDL, this TDC can provide high resolution with less hardware. The TDC works over the frequency of 1.2—1.8GHz, with a maximum power consumption of 2.5mW. The minimum resolution is 6.15ps and the maximum dynamic range is 1260ps. Thanks to the fine 6.14ps resolution, the calculated in-band phase noise of ADPLL is up to -113dBc/Hz performance.

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應用于全數(shù)字鎖相環(huán)中的精度可調的時間數(shù)字轉換器

張雪皎，崔科技，鄭立榮

(復旦大學 信息科學與工程學院， 上海 201203)

本文提出了一種應用于全數(shù)字鎖相環(huán)中的分辨率可調的兩級時間數(shù)字轉換器.第一級采用緩沖器延時鏈結構，運用可異步重置的觸發(fā)器作為采樣單元；第二級采用Vernier延時鏈結構以提高時間分辨率.和傳統(tǒng)的單級結構相比，兩級架構可以在更低的電路面積下實現(xiàn)相同的測量范圍，并提供更好的分辨率.為了降低工藝、電壓、溫度對分辨率的影響，本設計采用了電壓控制的延時單元，通過調整其延時來降低分辨率的變化.本設計通過65nm工藝驗證，總體面積0.06mm2.仿真結果表明，在輸入頻率為1.2～1.8GHz時，分辨率可達6.15ps，動態(tài)范圍1260ps，實現(xiàn)8bits時間數(shù)字轉換器，功耗僅2.5mW.

時間數(shù)字轉換器； 粗-細兩級架構； Vernier延時鏈； 可調諧分辨率

date：2015-03-30

Article ID：0427-7104(2016)02-0166-07

Biography：ZHANG Xuejiao (1990—), female, master; Corresponding author: ZHENG Lirong, professor, E-mail：lrzheng@fudan.edu.cn.