吳承勇 崔慧敏

摘 要：該報(bào)告針對Godson-D的芯片特征和億級并發(fā)負(fù)載的特征，研究了層次化MapReduce編程模型，對上層應(yīng)用呈現(xiàn)簡潔的編程接口，并利用OpenCL來開發(fā)Godson-D芯片的計(jì)算能力。對其中的3個關(guān)鍵問題進(jìn)行了闡述：形成了完整的層次化MapReduce編程模型的框架，并實(shí)現(xiàn)了原型系統(tǒng)，旨在解決現(xiàn)有MapReduce模型在多核/眾核芯片組成的集群中存在的性能墻、在適用場景方面存在的無法適應(yīng)增量式分析這兩個主要的問題；為了解決Godson-D上的編程困難問題，該研究提出使用OpenCL編寫程序，并配套開發(fā)CPU+Godson-D異構(gòu)系統(tǒng)中OpenCL編譯/運(yùn)行時系統(tǒng)的解決方案。在該研究中，首先完成了OpenCL編譯/運(yùn)行時支持系統(tǒng)的框架設(shè)計(jì)，該框架采用層次化設(shè)計(jì)思想，分為功能層、優(yōu)化層、平臺層；多核/眾核處理器及云計(jì)算被認(rèn)為將會統(tǒng)治計(jì)算領(lǐng)域的未來，多核/眾核處理器在目前的云計(jì)算數(shù)據(jù)中心中被廣泛采用，但是目前其資源利用率非常低，主要原因在于核間性能干擾的存在，使得數(shù)據(jù)中心的調(diào)度程序不得不禁止關(guān)鍵應(yīng)用的co-location來保證QoS，為此，提出了一種基于統(tǒng)計(jì)學(xué)習(xí)的多核間性能干擾分析方法，可以量化地分析任意程序遭受的核間性能干擾，并根據(jù)干擾模型提高資源的利用率。

關(guān)鍵詞：異構(gòu)集群 編程環(huán)境 異構(gòu)芯片 編譯技術(shù)

Abstract：Based on the chip architecture and the features of highly concurrent workloads， this report discussed the hierarchical MapReduce programming model， to expose a user-friendly programming interface and leverage OpenCL to take advantange of the computing power of Godson-D processor. This report presented three key ideas in detail：（1） Existing MapReduce programming model has two disadvantages： it cannot take advantage of the computing power of underlying multi/many-core processors， and it cannot adapt for increamental analysis. To address these two problems， we proposed the hierarchical MapReduce programming framework implements a prototype.（2） To provide a user-friendly programming interface for Godson-D， we proposed a OpenCL compiler/runtime system for Godson-D. We designed a hierarchical hetergeneous compiler/runtime system for Godson-D， which includes functional level， optimization level and platform level.（3） Despite their widespread adoption in cloud computing， multicore processors are heavily under-utilized in terms of computing resources. To avoid the potential for negative and unpredictable interference， co-location of a latency-sensitive application with others on the same multicore processor is disallowed， leaving many cores idle and causing low machine utilization. To enable co-location while providing QoS guarantees， it is challenging but important to predict performance interference between co-located applications.We proposed a regression approach to predict the interference and improve the resource utilization.

Key Words：Hertergeneous clusters；Programming enviornment；Hetergeneous chip；Compiler

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