ZHANG Rui，LIANG Ting*，XIONG Jijun，LIU Yutao，WANG Taolong，WANG Xinxin

(1.Key Laboratory of Instrumentation Science&Dynamic Measurement(North University of China)，Ministry of Education，Taiyuan 030051，China；2.Science and Technology on Electronic Test&Measurement Laboratory，North University of China，Taiyuan 030051，China)

A Piezoresistive SOI Pressure Sensor for Wide Measurement Range*

ZHANG Rui1，2，LIANG Ting1，2*，XIONG Jijun1，2，LIU Yutao1，2，WANG Taolong1，2，WANG Xinxin1，2

(1.Key Laboratory of Instrumentation Science&Dynamic Measurement(North University of China)，Ministry of Education，Taiyuan 030051，China；2.Science and Technology on Electronic Test&Measurement Laboratory，North University of China，Taiyuan 030051，China)

This paper focuses on structural design for optimizing sensitivity of traditional piezoresistive SOI pressure sensor to enhance measurement range in high-temperature environments.By modeling mechanical properties，a shallow-boss configuration is adopted for increasing sensitivity and measurement range.Key influence factors of sensitivity including boss thickness and shape are analyzed and simulated.Doping concentration，size of single piezoresistor，arrangement of metal wires and their material are obtained when taking into account device high-temperature performance.Piezoresistor location is arranged on the basis of taking full advantage of maximum（σl-σt）regions to maintain sensitivity and linearity.According to stress distribution of the diaphragm，U-shaped piezoresistors are finally adopted by considering sensitivity loss due to fabrication deviation of shallow bossed structure.Finite element analysis（FEA）results show that the optimum design enables the sensor chip to operate in wider pressure condition(within 10 MPa）with a high sensitivity of 86.6 mV/(V·MPa）and excellent nonlinearity is less than 0.1%.Compared with other current wide-range sensors，the strength of shallow central bossed structure lies in sensitivity and overload capacity.

wide measurement range；piezoresistive SOI pressure sensor；high temperature；finite element analysis(FEA)

Recently，there is a growing demand for high sensitivity sensor used in high-temperature environments to measure relatively wide-range pressure such as petrochemical industry，auto industry，etc［1］.Some efforts have been made to extent operation range of traditional MEMS piezoresistive pressure sensor.With the purpose of measurement extension，diaphragm thickness has to be thicker and sensitivity of the sensor chip will be affected.Therefore，the sensor structure needs to be optimized to increase the sensitivity of traditional flat diaphragm.

Bossed diaphragm has been mainly applicable forlower-pressure applications［2］.Advantage of a boss lies in improving linearity and overload of sensor remarkably with thin diaphragm thickness.This characteristic is also useful for improving operation range.In this article，a shallow bossed sensor structure aimed at wide measurement range is designed and simulated.SOI（silicon on insulator）has been widely used to fabricate high-temperature sensors for its excellent temperature property［3-4］.A piezoresistive SOI pressure sensor with a wider range of 0～10 MPa is designed based on commercial SOI wafer of SIMOX technology.Main factors of a piezoresistor including doping concentration，power and placement are carefully decided from the perspective of high temperature and characteristic of diaphragm structure.Output drift caused by metal wires in high-temperature environments is studied as well.The designed sensor is made by MEMS process.

1 Design and analysis of sensor structure

Fig.1 shows the schematic of proposed sensor chip structure.A full Wheatstone bridge constituted of four piezoresistors is used to measure stress of diaphragm and converts it to an electrical output signal.

Fig.1 Layout of sensor chip structure

The sensitivity of a piezoresistive pressure sensor is given by

Uinrepresents full scale input，PMrepresents maximum applied pressure and U(PM）is the corresponding output.To enhance the sensitivity，the only single variable—U(PM）should be studied.

Initially，R1=R3=R2=R4=R and thus the bridge output Uout=0.When pressure is exerted on surface of the chip，values of resistance change are approximately equal but have opposite signs and thus both types of piezoresistors can contribute to the bridge output.That is，ΔR1=ΔR4≈ΔR andΔR2=ΔR3≈-ΔR，which results in

πl(wèi)is longitudinal piezoresistive coefficient and πttransverse piezoresistive coefficient.σland σtare longitudinal stress［defined by Y in Fig.1］and transverse stress［defined by X in Fig.1］of the diaphragm，respectively.

From the equation（2)，it is obvious that piezoresistive coefficients and stresses values are contributed to influence factor of the sensitivity.The piezoresistive coefficients are mainly connected to resistance material including crystal orientation and doping concentration［5］，and the values of stresses are related to the chip structure and its shape.

To obtain the highest sensitivity，p-type singlecrystal SOI wafer is selected as piezoresistor material and four piezoresistors are arranged along＜110＞orientation.From both sensitivity and productivity considerations，the favored sensor chip shape is square［6-7］.A surface impurity concentration of 3×1018cm-3is chosen to reduce temperature sensitivity of piezoresistors and maintain a high piezoresistive coefficients［5］.

In〈110〉direction，Uoutcan be described as

Therefore，Uoutis proportional to differential stress（σl-σt）and sensitivity improvement of SOI pressure sensor requires（σl-σt）to be maximized.When a bossed diaphragm is used，difference effect of stresses and stiffness of the diaphragm can be enhanced［8］.Thus relatively good sensitivity and better linearity can be achieved，which is critical for wide-pressure range.

3 Simulation and optimization of diaphragm structure

Since analytical theory for calculating deformation and stress in the bossed diaphragm is complicated，ANSYS software is used for mechanical study of the chip structure.Dimensions for simulation is presented in Table 1.

Table 1 Dimension of the structure

Mechanical simulation of SOI sensor is a silicononly model with Young’s modulus of 1.69×1011Pa and Poisson’s ratio of 0.279，which for simplicity and speed of simulation.Clamping boundary is defined at bottom area of the structure.The simplified model is reasonable because the Young’s modulus of thin SiO2layer is low enough that its effect can be lumped in the silicon［9］.When higher pressure is exerted，the deflection of diaphragm may become nonlinear.Therefore，nonlinear simulation in ANSYS is necessary to guarantee feasibility of the design.Further simplification here also neglects depth of the piezoresistive regions.

Fig.2 Stress distribution on the sensor chip for an applied pressure of 10 MPa

Fig.2 shows stress distribution of the sensor chip for an applied pressure of 10 MPa with a 500 μm×500 μm×470 μm（l2×l3×h）boss.When the pressure rises to 10 MPa，maximum stress on the sensor chip is about 2120 MPa，which is less than the tensile ultimate stress of silicon rupture stress（7 000 MPa).Hence the diaphragm would not be fractured under the pressure of 10 MPa.Maximum（σl-σt）can be found at positions of x1=520 μm，x2=736 μm，x3=1264 μm and x4=1480 μm by path simulation，which are not exactly at the edges of clamping support and boss.To achieve high sensitivity，four piezoresistive elements should be placed in these four points separately.

The boss thickness and shape are also related to the sensor sensitivity and the overload capacity.Large boss will function as mobile mass of an accelerometer，which will increase additional acceleration sensitivity and eventually influence stability of diaphragm unpredictably［10］.To reduce difficulty and complexity of the measurement，the boss should be as thinner as possible.Fig.3 indicates that the less the thickness is，the more excellent sensitivity the chip will achieve.When nonlinear analysis of ANSYS has been taken into account，the chip with the boss thickness of only 25 μm can still guarantee a good linearity in the range of 10 MPa while that the center deflection of flat diaphragm changes nonlinearly.In addition，the linearity of the chip doesn’t be impaired apparently when overload pressures of 10 MPa to 20 MPa are applied.Therefore，a shallow-boss sensor structure can be loaded to wide range measurement for outstanding linearity，better sensitivity and proper overload pressure of at least 20 MPa.

Fig.3 Change of center deflection with different boss thicknesses

The boss shape depends on different aspect（l2/l3）ratios.Fig.4 shows how maximum differential stress values change when different aspect ratios of boss are applied.The thickness of the diaphragm is fixed as 180 μm.It is clear that the ranges of maximum（σl-σt）values are in the linear region for all kinds of boss aspect ratios.Tensile stresses can be increased proportionally with the decrease of aspect ratios.On the contrary，compressive stresses become almost the same since aspect ratios of boss reduce to 0.8.This means that the absolute stress values of tension and compression are no longer the same.A favored ratio should be 1（square shape）for equality of two kinds of stresses.

Fig.4 Change of maximum differential stress values with different aspect（l3/l2）ratios of boss

4 Design of piezoresistors and metal wires with high-temperature consideration

Not only doping concentration affect piezoresistors performance at high-temperature environment，but also heat generated by piezoresistors.To minimize the heat production，power consumption of piezoresistors should be small so that width of piezoresistors should be as broad as possible.Excitation voltage of the bridge is assumed 5 V and thus the original value for each piezoresistive element is 2.5 kΩ.

For the objective of high sensitivity，two pairs of piezoresistors are supposed to centralize in the regions of maximum difference of stresses as shown in Fig.1.Thus the width of piezoresistors should be thin since those high stress difference areas are narrow and focused.What’s more，longer and narrower the piezoresistor，larger the resistance will be obtained and current flow of piezoresistor will be one dimensional.An optimal ratio between the length and width of the piezoresistor should be ten［11］.After detailed consideration and weighing up the dimension，resistance and sensitivity，the width and length of the piezoresistor were decided to be 10 μm and 250 μm with Rs=100 Ω／口.To keep both high uniformity and sensitivity，piezoresistor with 2 turns（U shape）is more suitable than with 1 turn（straight shape).This is because that piezoresistors can be avoided to extend to areas of low stresses difference when utilizing U shape.

On the other hand，alignment of bossed structure photolithography and verticality during deep etching process always have deviation，so edge-offset is inevitable.Since the stresses are non-uniform and rapidly changing in maximum（σl-σt）locations，the location change of diaphragm edges will affect force situation of piezoresistors，which will influence the achievement of highest sensitivity in the end.U-shaped piezoresistor pattern can compensate this kind of edge-offset.Each piezoresistor is placed symmetrically cross its corresponding x-axis value，connected by multi metal with a space of 20 μm，so that the impact of edge-offset can be reduced greatly.The value of space should be small for the purpose of sensitivity，determining by maximum possible alignment error（±2 μm）and etching verticality error（±2°）in our laboratory，as Fig.1 plots.In addition，the doping uniformity of the centralized piezoresistors is better than piezoresistors diffused at the edge of the diaphragm，which can reduce output zero offset［1］.

Metal wires will easily be oxidized and have larger resistance at high-temperature environments.Ti-Pt-Au layers are sputtered on the surface of chip to solve the problem of oxidization for their good stability at high-temperature environments.As for resistance value change，it can be weaken by differential wires arrangement［12］.As Fig.1 illustrates，metal wires are placed symmetrically according to the diaphragm center with same size.Hence Equation（3）should be replaced by Equation（4)，defined as

ΔRmetalis the resistance change of wire for each single piezoresistor.It is far less than 1 Ω/100 K，leading to slight influence for bridge output.

5 Results and discussions

Table 2 is a comparison between proposed sensor and other types of wide-range sensors that has been reported［13-14］.It is obvious that the incorporation of shallow central bossed diaphragm with U-shaped piezoresistors can remarkably enhance sensitivity and overload capacity under wider range.Moreover，the optimized structure has an advantage of easy manufacture.From what has been discussed above，a SOI sensor of 10 MPa operation range with 180 μm boss thickness has been fabricated，as illustrated in Fig.5.

Table 2 Performance comparison with other types of wide-range sensors

Fig.5 Practical view of the fabricated pressure sensor

6 Conclusions

In this paper a high sensitivity piezoresistive SOI pressure sensors for 10 MPa range has been presented.The characteristic of the shallow square boss enables the optimum configuration to provide a wide measurement range with high sensitivity，excellent linearity and certain overload capacity through a series of ANSYS simulation.A centralized U-shaped piezoresistor design is an effective method to keep both sensitivity and uniformity of shallow bossed structure.High-temperature conditions is taken into account during the design procedure to satisfy high-temperature measurement request.By comparing with other types of widerange sensors that has been reported，it is concluded that the incorporation of shallow central bossed diaphragm with U-shaped piezoresistors could be an ideal candidate for wider-pressure and high-temperature sensing in real application.Based on the optimum design parameters，a piezoresistive SOI pressure sensor for wide measurement range has been successfully manufactured.Future work will be towards high-temperature testing of the proposed sensor.

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張 瑞（1990-），女，山西太原人，碩士研究生，研究方向?yàn)楦邷貕毫鞲衅鳎?5135088678@163.com；

梁 庭（1979-），男，山西長(zhǎng)治人，副教授、碩士生導(dǎo)師、博士，研究方向?yàn)楦邷貕毫鞲衅鳌EMS器件及工藝，liangtingnuc@163.com。

一種大量程SOI壓阻式壓力傳感器*

張 瑞1，2，梁 庭1，2*，熊繼軍1，2，劉雨濤1，2，王濤龍1，2，王心心1，2

（1.中北大學(xué)儀器科學(xué)與動(dòng)態(tài)測(cè)試教育部重點(diǎn)實(shí)驗(yàn)室，太原030051；2.中北大學(xué)電子測(cè)試技術(shù)國(guó)防科技重點(diǎn)實(shí)驗(yàn)室，太原030051）

對(duì)傳統(tǒng)的SOI壓阻式壓力傳感器進(jìn)行了結(jié)構(gòu)優(yōu)化。目的是提高靈敏度，以滿足在高溫環(huán)境下大量程壓力測(cè)量的實(shí)際需求。通過(guò)力學(xué)性能模擬，采用淺凸臺(tái)結(jié)構(gòu)來(lái)提高靈敏度和測(cè)量范圍。分析并模擬了凸臺(tái)厚度和形狀對(duì)靈敏度的影響。得到了適合高溫工作的摻雜濃度，壓敏電阻的尺寸，金屬引線的材料和布局。電阻放置在(σl-σt)最大的區(qū)域以保持靈敏度和線性度。采用U形電阻補(bǔ)償在淺凸臺(tái)制作過(guò)程中的工藝偏差對(duì)靈敏度的影響。有限元分析(FEA)表明，優(yōu)化后的芯片結(jié)構(gòu)可以測(cè)量10 MPa范圍內(nèi)的壓力，靈敏度高達(dá)86.6 mV/(V·MPa)，非線性誤差在0.1%以下。和其他文獻(xiàn)報(bào)道的大量程壓力傳感器相比，淺凸臺(tái)芯片結(jié)構(gòu)靈敏度和過(guò)載能力優(yōu)異。

大量程；SOI壓阻式壓力傳感器；高溫；有限元分析(FEA）

TP212

A

1004-1699(2015)08-1125-06

2015-04-20 修改日期：2015-06-08

??7230

10.3969/j.issn.1004-1699.2015.08.005

項(xiàng)目來(lái)源：The project is funded by the National Science Foundation for Distinguished Young Scholars of China（51425505)；National Natural Science Foundation of China（51405454）