YAO Qin-qin, XIE Rui, BAI Ru, SHEN Yu-ling

(Science and Technology on Electronic Test & Measurement Laboratory, North University of China, Taiyuan 030051, China)

?

Design of high-speed signal acquisition system and analysis of signal integrity

YAO Qin-qin, XIE Rui, BAI Ru, SHEN Yu-ling

(ScienceandTechnologyonElectronicTest&MeasurementLaboratory,NorthUniversityofChina,Taiyuan030051,China)

The device is used for the test on the fuze detonating time according to the initial velocity of the projectile and the altitude and speed of enemy aircraft flight. For the special requirements of the high-speed signal acquisition in the process, the characteristics of the measured signal are analyzed. The system is investigated in chip selection, signal transmission, signal processing, signal storage, post-production PCB design, etc. The appropriate measures and solutions which affect the integrity and accuracy of the signal in each process are proposed. The rules for the layout of the device and wiring are made. The result show that the measurement values are accurate without loss of data.

high-speed PCB simulation; data acquisition; signal integrity; static storage

In recent years, high-speed data acquisition technology has been widely used in radar, artillery, transient signal testing and other fields. In this paper, a kind of signal acquisition technology, dynamic programming, is presented[1]. Dynamic coding is carried out in the process of projectile launching. The frequency of the encoded signal ranges from 10 MHz to 50 MHz with the center frequency of 30 MHZ and the signal amplitude of 6 V. Based on the above characteristics, the acquisition system should be designed at the sampling frequency up to 500 MHZ and adjusted to the appropriate range with signal attenuation of 6 V. In addition, the system should have the characteristics of small volume and high impact resistance. However, for high-speed signal acquisition, not only the design requirements of general acquisition system should be met, but also the signal can not be affected in the process. Therefore, when designing, many factors should be considered, such as sequential design, signal attenuation, impedance matching, etc[2-10]. They are discussed in the following.

1 Hardware design

The high-speed signal acquisition system uses the Cyclone III FPGA as master chip. Analog-to-digital (A/D) conversion is realized by AD9484. The entire system can be divided into several modules according to the functions of signal conditioning, A/D conversion, data processing, data cache, static random access memory (SRAM) reading/writing, universal serial bus (USB) reading, etc. The structure block diagram of the system is shown in Fig.1.

The working process of the system is as follows. The system begins to work when receiving the external trigger signal after power on. The signal is attenuated by a tenth of the original signal by means of signal processing circuit to meet A/D input requirement. The signal is transmitted into A/D conversion circuit from signal processing circuit. Because A/D chip’s output is low voltage differential signaling (LVDS) mode, the matching network should transmit the signal into filed-programmable gate array (FPGA) accurately. FPGA receives high-speed LVDS data, process it and store it in cache memory. Then the data is written into SRAM under the control of the sequence. The signal acquisition is completed after all the data are stored in SRAM. After the projectile recycling, the data will be displayed on the soft panel of PC and analyzed under the control of CY7C68013 by means of USB interface.

Fig.1 Structure block diagram of high-speed signal acquisition system

2 Signal processing and storage by FPGA

In this system, FPGA not only achieves signal transmission based on LVDS interface with A/D, but also controls SRAM’s reading and writing. Therefore， data model should be converted by FPGA by directly calling IP core, altlvds_rx (RLVDS), in Quartus II[2-4]. In hardware design, AD9484 is connected by an LVDS interface with 10 channels. The string conversion coefficient is 1. The IP core completes the multi-channel synchronous parallel data receiving, string conversion and data buffering under the control of external clock. The internal working diagram of FPGA is presented in Fig.2.

To make the clock of SRAM and the converted data stream by A/D synchronous, the data bit in FPGA is extended. While the rising edge of the clock arrives, the 8 bit data are transmitted into the data buffer module I. After the next rising edge of the

clock arrives, the next 8 bit data is stored in data buffer module II and then is extended to a wider number of data bits to be output to SRAM. Thus, the output clock frequency can be reduced to half of the previous clock frequency, which makes SRAM be operated easily. Besides, because 18 bit data static storage is achieved in SRAM, the two 8 bit data can be stored in it, and thus the storage capacity of SRAM is improved. Fig.3 gives the simulation of the write timing of SRAM.

Fig.2 Logic working diagram inside FPGA

Fig.3 Simulation of write timing of SRAM

3 PCB design

Signal integrity is a key factor for system performance and some related factors should be considered when designing, including schematic design, printed circuit board (PCB) lamination, materials of transmission lines, distribution of power signal, etc. The optimal wiring scheme is chosen by simulation analysis of the key network and the problems of superimposition of signal integrity and precision integrity are solved by this method.

3.1 Signal integrity design

In the schematic, main impact factors on signal integrity are signal reflection and ground bouncing phenomena. For signal reflection, high-speed output signal lines (transmission lines) by AD9484 should be matched. There are so many components and transmission lines on PCB board that only the signal source performs impedance matching (termination resistors). Because the output resistance of source signal is small, a resistor connected in series with the signal line plays a role in impedance matching. While the input resistance of the receiver is very large, impedance matching is needed. However, the receiver in the system is under the control of FPGA from Cyclone III, considering the characteristics of FPGA, stacks 1, 2, 5 and 6 should be located in the left and

right ends of FPGA. Among these stacks, there are specialized output buffers, therefore, it need not perform impedance matching when they are used for output ports. But the upper and lower stacks of FPGA have not specialized output buffers. For any bank used for input port, it should use a resistor of 100 Ω for impedance matching. The topology of impedance matching network is shown in Fig.4.

Fig.4 Principle diagram of impedance matching network

Using the chips’ (IBIS) simulates the impact of the impedance matching. The input signal is pulse signal. The simulation results with impedance matching network and without impedance matching network are compared, as shown in Fig.5.

In Fig.5(a), without impedance matching network, distortion of output signal from U1 (AD9484) occurs and signal reflection phenomenon is obvious. The simulation results show that this method is valid. While in Fig.5(b), the quality of output signal from U1 is greatly improved and signal reflection phenomenon has been attenuated significantly.

Fig.5 Simulation results of reflection signal

3.2 PCB stackup and impedance control

An optimal design of PCB lamination can greatly reduce the control of impedance. For example, the impedance of transmission lines can be continuous rather than 50 Ω as the traditional impedance. Considering ball grid array (BGA) encapsulation processor in the device and the large number of components in PCB, a 4-layer PCB stackup is chosen, as shown in Fig.6.

Fig.6 4-layer PCB stackup design

In Fig.6, the top and the below layer are signal layers, the second layer is the formation and the third layer is the power supply layer. The dielectric constant is 4.5. Such stack program can suppress electromagnetic interference (EMI) of high-speed signal. The crosstalk between layers can be avoided by decreasing the thickness between the layers.

4 Experiment

The designed system is tested. Input signal is a 10 MHz sine wave. The experimental results are shown in Fig.7.

Fig.7 Test results of the system

As shown in Fig.7, X-axis displays the data points andY-axis is for quantitative amplitude. By moving cursor 1 at the beginning of a waveform and cursor 2 in the end of this waveform, it can be seen that the difference of cursor 1 and cursor 2 inX-axis direction is 50. Because the conversion rate of acquisition system is 500 million samples per second and the frequency of input signal is 10 MHz, the difference between the cursor 1 and 2 must be 50, which is the same as the result of the test. In Fig.7, the waveform distortion unlikely occurs and signal integrity is good.

5 Conclusion

This article presents a high-speed data acquisition and storage system. SI and timing are main problems when designing. Therefore, relevant factors are considered, including chip selection, signal transmission, signal processing, signal storage and PCB design and post-production, etc., aiming at drop the internal and the external interference down to a minimum. By experimental verification, the input impedance of the system reaches up to 1 mΩ which has little effect on the input signal, sampling precision can reach ±1.9 mV and the sampling rate is 500 million samples per second. Moreover, the system has been fixed into air guns. The test results show that the system is stable and easy to use.

[1] WANG Yong-zhen. The design of high-speed data acquistion and storage system. Master thesis. Taiyuan: North University of China, 2013.

[2] WANG Hao, WANG Zi-bing. Design of a 2 GSPS digital oscilloscope data acquisition system. Information and Electronic Engineering, 2009, 7(4)： 257-260.

[3] QU Yong-zhe, LI Yu-shan, YAN Xu, et al. Capacitive coupling connector and its signal integrity analysis. Journal of Xi-Dian University, 2011, 38(5)： 159-164.

[4] PENG Jun, LI Fu-hai, LUO Qi-wu. Design and implementation of a multi-channel parallel solid state storage system. Computer Engineering, 2013, 39(12)： 40-44, 59.

[5] YANG Zhen-jia, LIU Ying-jie, DENG Fang-fang. Design and implementation of high-speed signal acquisition storage and transmission system. Application of Electronic Technique, 2012, 38(9)： 8-10.

[6] QIN De-chun, CHEN Lei, PU You-zhu, et al. Method research of impedance matching based on analysis of signal integrity. Science Technology and Engineering, 2008, 8(4)： 1052-1055.

[7] RONG Shao-wei. Research of FPGA-based high-precision multi-channel acquisition and storage system. Electronic Measurement Technology, 2014, 37(4)： 108-111, 129.

[8] ZHANG Yong-qin, AI Yong, DENG De-xiang. Ultra-high speed data acquisition and processing system based on FPGA. Journal of Data Acquisition & Processing, 2009, 24(2)： 238-242.

[9] WANG Qiang, WEN Feng, REN Yong-feng. High-speed real-time data acquisition and storage system based on FPGA. Instrument Technique and Sensor, 2009, (1)： 50-52.

[10] ZHAO Yan-li, ZHEN Guo-yong, WEN Feng. The design of high-speed data acquistion and storage system based on FPGA. Electronic Technology, 2009, 46(1)： 18-20.

高速信號(hào)采集系統(tǒng)設(shè)計(jì)及信號(hào)完整性分析

姚琴琴， 謝 銳， 白 茹， 申玉玲

(中北大學(xué) 電子測(cè)試技術(shù)國(guó)家重點(diǎn)實(shí)驗(yàn)室， 山西 太原 030051)

本裝置根據(jù)實(shí)測(cè)彈丸的初速度和敵機(jī)飛行高度及航速、 航向?qū)σ诺钠鸨瑫r(shí)間進(jìn)行證測(cè)試。 針對(duì)中高速信號(hào)進(jìn)行采集的特殊要求， 通過(guò)對(duì)被測(cè)信號(hào)的特性分析， 結(jié)合系統(tǒng)的實(shí)際情況從芯片選擇、 傳輸方式、 信號(hào)處理以及后期的PCB設(shè)計(jì)制作等進(jìn)行分析。 對(duì)每個(gè)過(guò)程中可能出現(xiàn)的影響信號(hào)完整性和精準(zhǔn)性的干擾提出相應(yīng)的預(yù)防措施， 對(duì)系統(tǒng)PCB中部分關(guān)鍵網(wǎng)絡(luò)進(jìn)行仿真， 制定器件的布局布線約束。 實(shí)驗(yàn)驗(yàn)證本測(cè)量裝置可達(dá)到精準(zhǔn)測(cè)量、 無(wú)丟失數(shù)據(jù)。

高速PCB仿真； 數(shù)據(jù)采集存儲(chǔ)； 信號(hào)完整性； 靜態(tài)存儲(chǔ)

YAO Qin-qin, XIE Rui, BAI Ru, et al. Design of high-speed signal acquisition system and analysis of signal integrity. Journal of Measurement Science and Instrumentation, 2015, 6(1)： 63-67.

10. 3969/j. issn. 1674-8042.2015.01.012

YAO Qin-qin (15035168176@163.com)

1674-8042(2015)01-0063-05 doi： 10.3969/j.issn.1674-8042.2015.01.012

Received date： 2014-09-20

CLD number： TP911.7 Document code： A