陳定平+張忠華+李理+趙圣哲

摘要： 一些DMOS產(chǎn)品的Vfsd上限要求做得很低，這樣背金工藝的窗口就非常窄、經(jīng)常發(fā)生Vfsd超上限的事件。如何拓寬背金工藝窗口、滿足特殊DMOS產(chǎn)品對(duì)Vfsd的苛刻要求，在此研究了背面減薄、背面硅腐蝕和背面注入的主要工藝關(guān)鍵參數(shù)對(duì)Vfsd的影響。比較減薄機(jī)研磨輪目數(shù)后發(fā)現(xiàn)，研磨輪目數(shù)決定背面粗糙度，進(jìn)而影響背面SI與背面金屬的接觸電阻和Vfsd；比較硅腐蝕有、無活性劑后發(fā)現(xiàn)，加了活性劑的背面硅腐蝕速率溫和、均勻性好，可減緩切入式減薄機(jī)的Vfsd扇形分布、Vfsd均勻性明顯改善。背注能量拉偏后發(fā)現(xiàn)，降低背注能量可降低Vfsd的Mean值。綜合以上機(jī)理分析和實(shí)驗(yàn)結(jié)果，找到了背面最佳工藝條件，大大拓寬了背金工藝窗口。在最佳背面工藝條件下，這些特殊的DMOS產(chǎn)品Vfsd超上限幾率從1.5%下降到0.1%以下、良率平均上升4%，此背金最佳工藝可以成為DMOS生產(chǎn)的標(biāo)準(zhǔn)工藝。

關(guān)鍵詞： DMOS Vfsd超上限； 背面減??； 背面硅腐蝕； 表面活性劑； 背面注入

中圖分類號(hào)： TN710?34 文獻(xiàn)標(biāo)識(shí)碼： A文章編號(hào)： 1004?373X（2014）08?0072?03

Stduy of DMOS Vfsd′s backside process margin

CHEN Ding?ping， ZHANG Zhong?hua， LI Li， ZHAO Sheng?zhe

（Founder Microelectronics International Co.， Ltd.， Shenzhen 518116， China）

Abstract： Since some special DMOS products require very low Vfsd′s upper limit， the window of backside process becomes very narrow and the phenomenon of Vfsd upper limit happens quite often. To widen the window of backside process and satisfy the Vfsd requirement of special DMOS products， the influence of key parameters of main processes of backside grinding， backside Si wet etching and backside injection on Vfsd value is studied. According to the comparison result of backside grinding wheels with different mesh numbers， it is found that the mesh number of grinding wheel affects the roughness on the backside greatly， as well as the contact resistance between backside Si and backside metal. After comparing Si wet etching with and without active agent， it is found that surfactants injection can slow down Vfsds sector distribution and improve Vfsd uniformity obviously. To lowing down the backside injection energy can reduce Vfsds Mean value. BKM conditions of backside process were found out from the mechanism analysis and experiments results. Under BKM condition， special DMOS productss Vfsd ultralimit rate reduced from 1.5% to current 0.1% and CP yield increased 4%. This BKM process can be applied as standard process of DMOS production.

Keywords： DMOS Vfsd； Ultra?limit； backside grinding； backside Si wet etch； surfactant； backside implantation

DMOS產(chǎn)品生產(chǎn)中背金工藝[1]包含背面減?。˙ackside Grinding）、背面濕法硅腐蝕（Backside Si Wet Etch）、背面注入（Backside Implant）和背面蒸發(fā)金屬（Backside Implant）。其中背面減薄、背面濕法硅腐蝕、背面注入對(duì)DMOS Vfsd參數(shù)的影響最大[2]。

1Vfsd的概念

Vfsd（Forward Voltage of diode between S，D）源漏間的二極管正向?qū)▔航?。測(cè)量方法：GS短接，S接地，SD加偏壓Vsd，測(cè)量SD間電流Isd。增大Vsd，當(dāng)Isd達(dá)到設(shè)定值時(shí)的Vsd即為Vfsd；Vgs=0 V，Id=設(shè)定值（見圖1）。